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CAREER: Co-optimization of Integrated Circuit Design and Manufacturing

CAREER: Co-optimization of Integrated Circuit Design and Manufacturing
职业:集成电路设计与制造的协同优化
批准号:
0846196
负责人:
Puneet Gupta
金额:
$40.06万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-07-01 至 2014-06-30

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中文摘要
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英文摘要
Proposal ID: 0846196Title: CAREER: Co-optimization of Integrated Circuit Design and ManufacturingPI name: Puneet GuptaThis CAREER proposal aims to investigate methods for co-optimization of integrated circuit design and the manufacturing process for improved power, performance, yield, cost and turnaround time. The semiconductor industry is likely to see several radical changes in the fabrication and device technologies in the next decade. Each of these technologies requires enormous research investment before they can see any adoption. Conventional after-the-fact changes to design methodologies and tools to technology leads to wasted effort and under-utilization of technology. Therefore, this project focuses on early assessment of circuit design restrictions imposed by technological choices. ?Equivalent scaling? improvements - perhaps as much as one full technology generation - must come from new synergies between various ?silos? of the integrated circuit design to manufacturing flow. The PI plan on developing an algorithmic method of manufacturing process optimization driven by design analyses to significantly speed up yield ramp and improve product characteristics.Semiconductors have fueled wealth creation and technological revolution for better quality of life in the past few decades. The broader impact of the proposed research comes from enabling chip designers and manufacturers to co-develop future technologies for affordable, high-performance, high-density, low-power integrated circuits. My work will inform both the design technology and process technology roadmaps, so as to enable the electronics industry to derive maximum product benefit from underlying technology. The education component of the proposal will train a new breed of designers who are aware of process interactions and process/device engineers aware of design implications. The PI will leverage UCLA's extensive diversity and outreach resources to recruit students from female and underrepresented groups.
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会议论文
SHF: Small: Layout Assessment and Optimization for Disruptive Patterning and Device Technologies
CPA-DA Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing Optimizations
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