CAREER: Co-optimization of Integrated Circuit Design and Manufacturing

职业：集成电路设计与制造的协同优化

• 批准号: 0846196
• 负责人: Puneet Gupta
• 金额: $ 40.06万
• 依托单位: University of California-Los Angeles
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-07-01 至 2014-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0846196&HistoricalAwards=false
• 关键词: CAREER; Co; optimization; Integrated; Circuit

Proposal ID: 0846196Title: CAREER: Co-optimization of Integrated Circuit Design and ManufacturingPI name: Puneet GuptaThis CAREER proposal aims to investigate methods for co-optimization of integrated circuit design and the manufacturing process for improved power, performance, yield, cost and turnaround time. The semiconductor industry is likely to see several radical changes in the fabrication and device technologies in the next decade. Each of these technologies requires enormous research investment before they can see any adoption. Conventional after-the-fact changes to design methodologies and tools to technology leads to wasted effort and under-utilization of technology. Therefore, this project focuses on early assessment of circuit design restrictions imposed by technological choices. ?Equivalent scaling? improvements - perhaps as much as one full technology generation - must come from new synergies between various ?silos? of the integrated circuit design to manufacturing flow. The PI plan on developing an algorithmic method of manufacturing process optimization driven by design analyses to significantly speed up yield ramp and improve product characteristics.Semiconductors have fueled wealth creation and technological revolution for better quality of life in the past few decades. The broader impact of the proposed research comes from enabling chip designers and manufacturers to co-develop future technologies for affordable, high-performance, high-density, low-power integrated circuits. My work will inform both the design technology and process technology roadmaps, so as to enable the electronics industry to derive maximum product benefit from underlying technology. The education component of the proposal will train a new breed of designers who are aware of process interactions and process/device engineers aware of design implications. The PI will leverage UCLA's extensive diversity and outreach resources to recruit students from female and underrepresented groups.

提案ID：0846196职务：职业：集成电路设计和制造的共同优化PI姓名：Puneet Gupta该CAREER提案旨在研究集成电路设计和制造工艺的共同优化方法，以提高功率，性能，产量，成本和周转时间。在未来十年，半导体行业可能会在制造和器件技术方面发生一些根本性的变化。这些技术中的每一项都需要大量的研究投资，然后才能看到任何采用。传统的设计方法和工具到技术的事后更改导致浪费精力和技术利用不足。因此，本项目的重点是对技术选择所带来的电路设计限制进行早期评估。?等效缩放？改进-也许相当于一个完整的技术世代-必须来自各种不同的技术之间的新的协同作用。筒仓？从集成电路设计到制造流程。PI计划开发一种由设计分析驱动的制造过程优化算法，以显著加快产量上升并改善产品特性。在过去的几十年里，半导体推动了财富创造和技术革命，提高了生活质量。拟议研究的更广泛影响来自于使芯片设计师和制造商能够共同开发负担得起的，高性能，高密度，低功耗集成电路的未来技术。我的工作将为设计技术和工艺技术路线图提供信息，从而使电子行业能够从基础技术中获得最大的产品效益。该提案的教育部分将培养一批新的设计师，他们意识到工艺相互作用和工艺/设备工程师意识到设计的影响。PI将利用加州大学洛杉矶分校广泛的多样性和外联资源，从女性和代表性不足的群体中招募学生。