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CAREER: Co-optimization of Integrated Circuit Design and Manufacturing

CAREER: Co-optimization of Integrated Circuit Design and Manufacturing
职业:集成电路设计与制造的协同优化
批准号:
0846196
负责人:
Puneet Gupta
金额:
$40.06万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-07-01 至 2014-06-30

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中文摘要
翻译
提案ID:0846196标题:Career:集成电路设计和制造的共同优化PI名称:Puneet Gupa这份职业提案旨在研究集成电路设计和制造流程的联合优化方法,以提高功率、性能、产量、成本和周转时间。在接下来的十年里,半导体行业很可能会在制造和器件技术上看到几个根本性的变化。这些技术中的每一项都需要巨大的研究投资,才能看到任何采用。传统的设计方法和工具对技术的事后更改导致浪费精力和技术未得到充分利用。因此,本项目的重点是早期评估技术选择对电路设计的限制。?等量缩放?改进--也许多达一代完整的技术--必须来自不同竖井之间的新协同效应?从集成电路设计到制造流程。PI计划开发一种由设计分析驱动的制造过程优化的算法方法,以显著加快良率增长并改善产品特性。在过去的几十年里,半导体推动了财富创造和技术革命,以提高生活质量。拟议研究的更广泛影响来自于使芯片设计者和制造商能够共同开发负担得起的、高性能、高密度、低功耗集成电路的未来技术。我的工作将为设计技术和工艺技术路线图提供信息,使电子行业能够从底层技术中获得最大的产品效益。该提案的教育部分将培训新一代的设计师,他们意识到工艺相互作用,工艺/设备工程师意识到设计的影响。PI将利用加州大学洛杉矶分校广泛的多样性和外展资源,从女性和代表性不足的群体中招收学生。
英文摘要
Proposal ID: 0846196Title: CAREER: Co-optimization of Integrated Circuit Design and ManufacturingPI name: Puneet GuptaThis CAREER proposal aims to investigate methods for co-optimization of integrated circuit design and the manufacturing process for improved power, performance, yield, cost and turnaround time. The semiconductor industry is likely to see several radical changes in the fabrication and device technologies in the next decade. Each of these technologies requires enormous research investment before they can see any adoption. Conventional after-the-fact changes to design methodologies and tools to technology leads to wasted effort and under-utilization of technology. Therefore, this project focuses on early assessment of circuit design restrictions imposed by technological choices. ?Equivalent scaling? improvements - perhaps as much as one full technology generation - must come from new synergies between various ?silos? of the integrated circuit design to manufacturing flow. The PI plan on developing an algorithmic method of manufacturing process optimization driven by design analyses to significantly speed up yield ramp and improve product characteristics.Semiconductors have fueled wealth creation and technological revolution for better quality of life in the past few decades. The broader impact of the proposed research comes from enabling chip designers and manufacturers to co-develop future technologies for affordable, high-performance, high-density, low-power integrated circuits. My work will inform both the design technology and process technology roadmaps, so as to enable the electronics industry to derive maximum product benefit from underlying technology. The education component of the proposal will train a new breed of designers who are aware of process interactions and process/device engineers aware of design implications. The PI will leverage UCLA's extensive diversity and outreach resources to recruit students from female and underrepresented groups.
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会议论文
SHF: Small: Layout Assessment and Optimization for Disruptive Patterning and Device Technologies
CPA-DA Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing Optimizations
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