AitF: EXPL: Data Management in Domain Wall Memory-based Scratchpad for High Performance Mobile Devices

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To achieve scalable performance improvement in mobile devices such as smart phones, it is important to integrate a larger and faster memory. The major constraints on enlarging on-chip memory using traditional memory technologies are size and energy efficiency. Size is an issue because devices must inherently be small to be mobile. Energy efficiency is an issue because battery life is often the limiting factor in the usefulness of mobile devices, and the memory subsystem in mobile devices such as smart phones can consume about a third of the total energy. Because of these limitations, the amount of memory per processor in mobile devices such as smart phones has stayed relatively stable over the last few generations of technologies. The incorporation of the emerging technology of Domain Wall Memory in mobile devices is attractive as it can store more information in less volume than any competing technologies, while simultaneously using little energy, and being nearly as fast as traditional memory technologies.However, Domain Wall Memory has physical properties that are different than traditional memory technologies, and that can potentially impact performance. In particular, Domain Wall Memory is divided into tracks, which like a tape, may only be accessed sequentially. Thus accessing two data items stored far apart within the same track will be a costly, time-consuming operation. Thus obtaining the best possible performance of Domain Wall Memory will require algorithms/solutions that will smartly manage the placement of data items into memory so that the sequential access properties of Domain Wall Memory do not significantly degrade performance. The goal of the project is to design, analyze, test and deploy algorithms/solutions for data allocation problems that will arise with the adoption of Domain Wall Memory in mobile devices. As these data management problems have unique features, the development of algorithms for these problems will likely require the development of new algorithmic design and analysis techniques. Developing a good practical implementation of these algorithms, or implementations inspired by these algorithms, will require the development of a significant understanding of both implementation issues and common instance properties. The project will cross-train students in the area of computer architecture and algorithms. Transfer of technology to the industry will bepursued through collaborations and visits.It is promising to incorporate Domain Wall Memory as a software-controlled scratchpad memory, which has been widely adopted in embedded systems for achieving high performance and energy efficiency. For data items allocated in the same Domain Wall Memory track, accesses start with shifting the target domains below the head, which is similar to accesses to sequential access memory such as tape and hard drives. The overhead to access a data item includes both the read/write overhead and the shift overhead. While the former is constant, the latter depends heavily on how the data items are allocated within the track. Thus optimizing aggregate access time in DWM-SPM largely involves minimizing shifts. The performance of DWM-SPM will be significantly affected by the policies used for: (a) Track management: How the data items are organized/ordered within a track, (b) Data layout: How the data items are assigned to tracks, and (c) Data selection: How the data items that will be stored in DWM-SPM are selected.The project will design and formally analyze algorithms for track management, data layout, and data selection in idealized models of Domain Wall Memory. The advantage of formal algorithmics is that the formal objective can drive the discovery of non-intuitive algorithms. Concurrent with this theoretical investigation, a simulation environment will be created to test proposed solutions to managing Domain Wall Memory. This includes the assembly of hardware modeling tools, software simulators, and a collection of benchmark programs. The project will develop and implement some simple policies to serve as a baseline to compare against, and obtain test instances representative of those that would arise in practice, and will transfer the theoretical insights into actual implementations. These implementations would then be compared to the baseline and greedy heuristic solutions.