Enabling Algorithms, Signal Processing, and Circuits for Agile Cognitive Radio in CMOS Technology

认知无线电技术将被开发，使其能够在存在强干扰的情况下进行快速、宽带频谱感知。认知无线电必须快速、实时、高成功率地检测可用频谱，这要求在存在强大干扰信号的情况下具有极高的动态范围。此外，未来的认知无线电将在广泛的频率范围内的多个频段上运行。这增加了接收器设计的挑战，因为所有的滤波都必须能够在宽频率范围内调谐。最后，无线电必须灵活地在频段之间跳跃。检测任何信道中的功率所需的时间是限制网络吞吐量的开销。大多数先前的认知无线电研究将数字基带算法应用于传统的射频和模拟无线电电路，这不是为了解决频谱感知应用而设计的。这限制了可实现的频谱感知带宽和灵活性，并导致RF、模拟和数字信号处理模块的高功耗。这项工作的根本不同之处在于，它将定制从射频电路到数字信号处理(DSP)的整个接收链，以结合专门针对频谱感知的新技术。这些技术包括向接收器注入伪噪声调制的RF信号，以通过DSP中的相关算法识别阻塞器，以及校准和消除接收器的非线性特性。我们将开发和改进所提出的算法，并在28 nm的CMOS接收器集成电路中演示它们的实用性。

Cognitive radio techniques will be developed that enable rapid, wideband spectrum sensing in the presence of strong interference. Cognitive radios must detect available spectrum quickly in real time with high-probability of success, which requires extremely high dynamic range in the presence of powerful interference signals. Furthermore, future cognitive radio will operate over multiple frequency bands spread out over a wide frequency range. This compounds the challenges to the receiver design since all filtering must be capable of tuning over wide frequency ranges. Finally, the radio must agilely hop among frequency bands. The time required to detect the power in any channel is an overhead that limits the network throughput.Most prior cognitive radio research applies digital baseband algorithms to conventional RF and analog radio circuitry, which is not designed to address the spectrum sensing application. This limits the achievable spectrum sensing bandwidth and agility and results in high power consumption for the RF, analog, and digital signal processing blocks. This work is fundamentally different in that it will customize the entire receive chain from the RF circuitry through the digital signal processing (DSP) to incorporate new techniques specifically targeted to address spectrum sensing. The techniques involve the injection of pseudonoise-modulated RF signals into the receiver to identify the blockers via correlation algorithms in the DSP as well as to calibrate and cancel the nonlinear characteristics of the receiver. We will develop and refine the proposed algorithms and demonstrate their utility in a 28-nm CMOS receiver integrated circuit.