Plesiochronous Communication for Silicon-Constrained High-Speed Serial Links

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This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).The objective of this research is to demonstrate energy efficient, mixed-signal silicon transceiver circuitry using time-domain signal modulation for high-speed serial links. The approach is to employ plesiochronous double-edge pulse-width modulation to achieve higher data rates than traditional pulse amplitude modulation over a given interconnect. A 90-nanometer silicon mixed-signal transceiver circuit will be invented and fabricated to verify the channel and source coding approach.Intellectual Merit: This research investigates optimal signaling subject to interconnect bandwidth and peak power constraints imposed by highly scaled silicon integrated circuit processes. Performance improvements will be achieved by combining both advances in CMOS circuit design and communication theory to address the physical constraints of deep submicron CMOS and the adverse effects of the transmission channel. Broader Impacts: This project addresses energy savings in server and computer communication. It is estimated that more than one gigaWatt of power is required worldwide to power the high-speed serial links that exchange data between microprocessors and memory and enable the benefits of networking and computing for work, entertainment, and social interaction. The outcomes of this research advance a global technology concern, and coincident educational efforts will teach and train students about the interaction of energy and technology and how circuit design addresses the need for low power computation and communication. The project will train a Ph.D. student and includes outreach activities to middle and high school students through active mentorship.