Plesiochronous Communication for Silicon-Constrained High-Speed Serial Links

用于硅约束高速串行链路的准同步通信

• 批准号: 0901273
• 负责人: James Buckwalter
• 金额: $ 32.37万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2013-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0901273&HistoricalAwards=false
• 关键词: Plesiochronous; Communication; Silicon; Constrained; Speed

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).The objective of this research is to demonstrate energy efficient, mixed-signal silicon transceiver circuitry using time-domain signal modulation for high-speed serial links. The approach is to employ plesiochronous double-edge pulse-width modulation to achieve higher data rates than traditional pulse amplitude modulation over a given interconnect. A 90-nanometer silicon mixed-signal transceiver circuit will be invented and fabricated to verify the channel and source coding approach.Intellectual Merit: This research investigates optimal signaling subject to interconnect bandwidth and peak power constraints imposed by highly scaled silicon integrated circuit processes. Performance improvements will be achieved by combining both advances in CMOS circuit design and communication theory to address the physical constraints of deep submicron CMOS and the adverse effects of the transmission channel. Broader Impacts: This project addresses energy savings in server and computer communication. It is estimated that more than one gigaWatt of power is required worldwide to power the high-speed serial links that exchange data between microprocessors and memory and enable the benefits of networking and computing for work, entertainment, and social interaction. The outcomes of this research advance a global technology concern, and coincident educational efforts will teach and train students about the interaction of energy and technology and how circuit design addresses the need for low power computation and communication. The project will train a Ph.D. student and includes outreach activities to middle and high school students through active mentorship.

该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的。本研究的目的是展示使用时域信号调制的高速串行链路的节能混合信号硅收发器电路。该方法是采用准双沿脉冲宽度调制，以实现更高的数据速率比传统的脉冲幅度调制在给定的互连。一个90纳米的硅混合信号收发器电路将发明和制造，以验证信道和源代码approach.Intellectual优点：这项研究探讨最佳的信令互连带宽和峰值功率的高度扩展的硅集成电路工艺所施加的限制。通过结合CMOS电路设计和通信理论的进步来解决深亚微米CMOS的物理约束和传输通道的不利影响，将实现性能的改善。 更广泛的影响：该项目解决了服务器和计算机通信的节能问题。 据估计，全世界需要超过1千兆瓦的功率来为高速串行链路供电，这些链路在微处理器和存储器之间交换数据，并使网络和计算能够为工作、娱乐和社交互动带来好处。这项研究的成果推动了全球技术的关注，同时教育工作将教授和培训学生关于能源和技术的相互作用，以及电路设计如何满足低功耗计算和通信的需求。该项目将培养一名博士。该方案还包括通过积极的指导活动向初中和高中学生开展外联活动。