EAGER: Novel Memory Design with Ballistic Deflection Transistors

由于系统的过度功耗和差的功率效率，使用常规硅技术构建兆级计算系统是禁止的。计算机系统消耗的大部分功率归因于存储器的操作。此外，嵌入式存储器通常占据微处理器面积的80%。需要实现在速度、功耗和集成密度方面提供显著（数量级）改进的新技术。 目前，下一代电路技术还没有明确的赢家;然而，基于量子传输的纳米级器件和结构是选择之一。在这一类中，在室温下操作的弹道传输纳米结构正在获得动力。弹道偏转晶体管（BDT）技术提供了皮秒级纳米级存储器设计机会。该项目的目标是研究在更大规模上集成皮秒BDT存储器的物理和限制，以及对制造，实验表征和物理建模的影响。 该项目为从事该项目的学生提供材料科学，器件物理，纳米制造和先进电子学的跨学科培训。该项目将为超快纳米级锁存器和存储器的设计中的转型概念和想法铺平道路，从而实现nxt代计算能力的exascale努力。它包括器件物理和建模，新颖的架构，并涵盖四个重点领域和一个特殊的演示项目：（1）使用基于具有非线性电导率的介质中的载流子传输的弹道迁移率概念来建模弹道纳米器件和电路，（2）纳米级弹道偏转晶体管（BDT）的制造和表征及其作为THz-开关集成到存储器电路中的数字电路元件;（3）用于存储器单元控制的BDT访问开关的概念的开发;以及4）基于弹道纳米器件的亚皮秒（THz带宽）BDT RAM单元设计操作的早期概念的研究。新存储单元的概念将彻底改变数据存储系统。 为了证明概念的可行性，将制造包括源极端子、两个栅极端子和三个漏极端子的六端子弹道偏转晶体管，在其中心具有三角形形状的偏转器。偏转器将以其左、右和顶（底）顶点分别指向BDT的左漏极端子、右漏极端子和源极端子的方式放置。该共面结构将被蚀刻到InGaAs 2DEG中。电子将从BDT的源极端子进入沟道。左输入栅极和右输入栅极将用于分别将电子导向左漏极端子和右漏极端子。顶部漏极将用于改变电子速度。在与中心偏转器碰撞时，电子将获得它们的动量以朝向输出漏极端子快速移动。如果成功，该项目将彻底改变能够支持下一代计算需求的exascale的现代存储器的性能和功率效率。

Building exascale computing systems using conventional silicon technology is prohibitive due to the excessive power consumption and poor power efficiency of the system. The majority of the power consumed by a computer system is attributed to the operation of the memory. In addition, embedded memories typically occupy up to 80% of the area of the microprocessor. The realization of new technologies that offer significant (orders of magnitude) improvements in speed, power consumption, and integration densities is needed. Presently there is no clear winner for next-generation circuit technology; however, nanoscale devices and structures based on quantum transport is one of the choices. In this category, ballistic transport nanostructures operational at room temperature are gaining momentum. Ballistic Deflection Transistor (BDT) technology offers picosecond nanoscale memory design opportunities. The goal of this project is to investigate the physics and limitations of integrating picosecond BDT memories on a larger scale and the impact on fabrication, experimental characterization, and physical modeling. The project offers students working on the project interdisciplinry training in material science, device physics, nanofabrication, and advanced electronics. This project will pave the way to transformational concepts and ideas in design of ultrafast nanoscale latches and memories, enabling efforts towards exascale for nxt generation of computing capabilities. It encompasses device physics and modeling, novel architectures, and covers four focus areas and a special demonstration project: (1) Modeling of ballistic nanodevices and circuits using the ballistic mobility concept based on carrier transport in media with nonlinear conductivity, (2) Fabrication and characterization of nano-scale ballistic deflection transistors (BDTs) and their implementation as THz-switching digital circuit elements integrated into memory circuits; (3) Development of the concept of BDT access switches for memory cell control: and 4) Investigation of early concepts of Sub-picosecond (THz bandwidth) BDT RAM cell design operation based on ballistic nanodevices. The concept of a new memory cell will revolutionize data storage systems. To prove the feasibility of concept, a six terminal ballistic deflection transistor comprising a source terminal, two gate terminals and three drain terminals will be fabricated, with a triangular shape deflector in its center. The deflector will be placed in such a way that left, right and top (bottom) vertex of it is pointed towards the left drain terminal, right drain terminal and source terminal of BDT respectively. This coplanar structure will be etched into an InGaAs 2DEG. The electrons will enter the channel from the source terminal of BDT. The left and right input gates will be used to steer the electrons towards left and right drain terminals respectively. The top drain will be used to change the electron velocity. Upon collision with central deflector, electrons will gain their momentum to move quickly towards the output drain terminals. If successful, the project will revolutionize the performance and power efficiency of modern memories capable of supporting exascale for next generation computing needs.