CAREER: Trading Communication and Storage for Computation to Enhance Energy Efficiency

展望未来，计算机系统中的一个根本挑战是电源墙，在那里，由于技术扩展的不平衡，并不是所有芯片上的计算引擎都能同时供电。Power Wall正在改变系统堆栈的所有级别，包括并行体系结构。由数据移动及其协调引起的通信能力以及存储能力主导着计算能力。随着并发性程度的提高，由于更频繁的数据传输，通信能力变得更加突出。与此同时，新兴的内存技术还不够成熟，无法在紧张的电力预算中跟上相应的容量、带宽和性能要求。健忘处理器可以最小化(如果不是消除)与数据存储、检索和通信相关的功率和性能开销，从而更有效地运行能量。健忘机的有限存储代表了短期记忆，这种记忆从结构上来说缺乏长期记忆。与经典机器相比，健忘机可以促进更多的计算引擎占据曾经专门用于(长期)记忆的区域，可以进一步利用这些区域进行重新计算。重新计算可以透明地转换工作负载，使其变得更加计算密集型，以便他们可以更好地利用针对性能而不是能效进行优化的传统架构。本项目意在解锁健忘机的能效前提。为此，PI建议探索编译器和微体系结构支持，以决定何时将远程加载替换为重新计算。这项研究有三个主要目的：(I)在编译时，将执行基于整数线性规划的优化，以生成概率能量最小重新计算时间表；(Ii)运行时控制器将被设计为根据编译器提供的信息来决定何时重新计算；以及(Iii)存储器层次结构也将被探索以最大限度地提高能量效率。还将考虑与新兴技术的互动和可靠性问题。综合教育和外展计划包括工作坊组织、本科课程和尤里卡！为K-12女孩提供的方案。

Looking forward, a fundamental challenge in computer systems is the Power Wall, where, due to imbalances in technology scaling, not all the compute engines that find place on chip can be powered on at the same time. The Power Wall is transforming all levels of the system stack, including the parallel architecture landscape. Communication power, as induced by data movement and the orchestration thereof, along with storage power, dominates computation power. As the degree of concurrency increases, communication power becomes even more prominent due to more frequent data transfers. At the same time, emerging memory technologies are not mature enough to keep up with the corresponding capacity, bandwidth, and performance requirements within a tight power budget. An amnesic processor, can minimize, if not eliminate, the power and performance overhead associated with data storage, retrieval, and communication, thus, operate more energy efficiently. The limited storage of the amnesic machine represents the short-term memory, which lacks long-term memory by construction. When compared to its classic counterparts, an amnesic machine can facilitate more compute engines to occupy the area once devoted to (long-term) memory, which can further be harnessed for recomputation. Recomputation can transparently convert workloads to become more compute intensive such that they can make a better use of classic architectures optimized for performance, as opposed to energy efficiency. This project intends to unlock the energy efficiency premise of amnesic machines. To this end, the PI proposes to explore compiler and microarchitecture support to decide when to replace remote loads with re-computation. The research has three major thrusts: (i) at compiler time, integer linear programming based optimization will be performed to generate a probabilistic energy-minimal re-computation schedule; (ii) runtime controller will be designed to decide when to re-compute based on the information the compiler provides; and (iii) memory hierarchy will also be explored to maximize energy efficiency. Interaction with emerging technologies and reliability issues will also be considered. The integrated education and outreach plan includes workshop organization, undergraduate curriculum, and Eureka! program for K-12 girls .