Collaborative Research: Approximate Computing on Real World Data Using Representation and Coding

传统晶体管缩放带来的好处减少的同时，数据生成速度却出现了压倒性的增长。专家分析显示，2011年，生成的数据量超过1.8 Zeta字节，并将在2020年前增长50倍。为了克服这些挑战，半导体行业和研究界都在探索计算领域的新途径。其中两种很有前途的方法是加速和近似。在加速器中，图形处理单元提供了重要的计算能力。最初旨在加速图形功能的图形处理单元，现在正在处理从传感器、雷达、环境、金融市场和医疗设备收集的大量真实世界数据。由于图形处理单元在加速许多类别的应用程序方面发挥着重要作用，因此提高它们的性能和能效已成为当务之急。该项目利用了这样一个事实，即许多受益于图形处理单元的应用程序容易受到不精确计算的影响。这一特性提供了设计近似技术的机会，该技术以输出质量的微小损失换取性能和能源效率的显著提高。这个项目旨在利用这一机会，并开发一个全面的框架，在图形处理单元的近似，以及有效的质量控制机制的基础上编码理论。能效可以说是计算机行业面临的最大挑战。为了保持美国在该行业的经济领导地位，至关重要的是开发解决方案，如该项目，以应对节能计算的根本挑战。计算行业已经到达了一个时代，在这个时代，许多创新技术，如这项工作，跨越了包括计算机体系结构、信息理论和信号处理在内的多个学科的边界。因此，培养一支不仅深刻理解多名门徒，而且能够跨越他们的边界进行创新的员工队伍是当务之急。该项目为此类教育和研究提供了基础。该项目将产生基准、工具和通用基础设施。这些文物将被公开提供，并将被整合到佐治亚理工学院和哈佛大学的课程中。为了转让这些技术，原则调查员已经与几家公司建立了密切联系。除了学者传播成果的惯常途径外，首席调查员还将继续组织关于近似计算的讲习班。这位首席研究员还在合著一本关于近似计算的书，其中将包括这个项目的结果。调查人员致力于本科生、代表性不足的学生和高中生的多样性和包容性，目前正在指导所有群体的学生，这将继续贯穿整个项目。该项目将首先为图形处理单元开发加速体系结构，该体系结构利用近似算法转换以实现更快和更节能的执行。其核心思想是使用神经模型来学习代码区域的行为，并用紧密集成在图形处理单元的多个核心中的硬件加速器取代该区域。其次，受香农的工作和随机码在噪声信道上提供可靠通信的成功的启发，这项工作将设计出利用编码技术来减少不精确度的质量控制解决方案。该码是隐含的，因为每当必须改进近似输出时，就利用其与可用的精确输出的相关性来构造和解码该码。第三，该项目将研究利用真实世界数据中固有的相似性和可预测性来解决图形处理单元中的内存瓶颈的机制。其主要思想是当数据加载操作在本地片上高速缓存中未命中时预测其值，并继续计算，而不等待来自片外存储器的长等待时间响应。为了进行有效的预测，本项目将利用我们新的模型匹配理论，为输入数据开发多区域自适应非线性时变动力学模型。

The diminishing benefits from traditional transistor scaling has coincided with an overwhelming increase in the rate of data generation. Expert analyses show that in 2011, the amount of generated data surpassed 1.8 zeta bytes and will increase by a factor of 50 until 2020. To overcome these challenges, both the semiconductor industry and the research community are exploring new avenues in computing. Two of the promising approaches are acceleration and approximation. Among accelerators, Graphic Processing Units provide significant compute capabilities. Graphic Processing Units, originally designed to accelerate graphics functions, now are processing large amounts of real-world data that are collected from sensors, radar, environment, financial markets, and medical devices. As Graphic Processing Units play a major role in accelerating many classes of applications, improving their performance and energy efficiency has become imperative. This project leverages the fact that many applications that benefit from Graphic Processing Units are amenable to imprecise computation. This characteristic provides an opportunity to devise approximation techniques that trade small losses in the output quality for significant gains in performance and energy efficiency. This project aims to exploit this opportunity and develop a comprehensive framework for approximation in Graphic Processing Units along with effective quality control mechanisms based on coding theory. Energy efficiency is arguably the biggest challenge of the computing industry. To maintain the nation's economic leadership in this industry, it is vital to develop solutions, such as this project, that address the fundamental challenges of energy-efficient computing. The computing industry has reached an era in which many of the innovative techniques, such as this work, crosses the boundary of multiple disciplines, including computer architecture, information theory, and signal processing. Thus, it is imperative to educate a workforce that not only deeply understands multiple disciples, but also can innovate across their boundaries. This project provides a foundation for such education and research. This project will produce benchmarks, tools and general infrastructure. These artifacts will be made publicly available and will be integrated in the Georgia Tech and Harvard curricula. To transfer these technologies, the principle investigators have established close contacts with several companies. Besides the customary routes academics use to disseminate results, the principle investigator will continue organizing workshops on approximate computing. The principle investigator is also coauthoring a book on approximate computing, which will include results from this project. The investigators are committed to diversity and inclusion of undergraduate, underrepresented, and high school students and are currently mentoring students from all groups that will continue throughout this project. This project will first develop an accelerated architecture for Graphic Processing Units, which leverage an approximate algorithmic transformation for faster and more energy efficient execution. The core idea is to use neural models to learn how a region of code behaves and replace the region with a hardware accelerator that is tightly integrated within the many cores of the Graphic Processing Units. Second, inspired by Shannon's work and the success of random codes in providing reliable communication over noisy channels, this work will devise quality control solutions that utilize coding techniques to reduce the imprecision. The code is implicit in a sense that whenever an approximate output must be improved, its correlation with available exact outputs is exploited for constructing and decoding the code. Third, the project will study mechanisms that leverage the inherent similarity and predictability in the real-world data to address the memory bottlenecks in Graphic Processing Units. The main idea is to predict the values of a data load operation when it misses in the local on-chip cache and continue the computation without waiting for the long-latency response from the off-chip memory. To perform effective prediction, this project will develop multi-regime adaptive nonlinear time-varying dynamical models for the input data using our new theories of model matching.