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CCF-BSF:SHF: Small: Timing Validation for Asyncronous Circuits

CCF-BSF:SHF: Small: Timing Validation for Asyncronous Circuits
CCF-BSF:SHF:小:异步电路的时序验证
批准号:
1617945
负责人:
Rajit Manohar
金额:
$35.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2016
资助国家:
美国
项目状态:
已结题
起止时间:
2016-08-01 至 2017-04-30
关键词:

项目摘要

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中文摘要
翻译
在先进材料、纳米制造和数字计算的研究和发展的推动下,低成本、高性能和低功耗的电子元件已经产生了智能手机、无线连接、高吞吐量网络、廉价数据中心,这只是我们现代数字经济的几个方面。然而,随着目前的技术接近物理定律的极限,性能和功率效率的提高不再是通过传统技术实现的。让多样化的学生群体接受非传统方法的培训是至关重要的,这样他们就可以把新的想法作为半导体行业的一部分来实践,并继续过去几十年被称为摩尔定律的惊人增长。异步电路和系统设计,在这个项目中,是一种非常规的方法,被研究作为一种提高计算效率的方法。该项目还与以色列两国科学基金会(BSF)合作,利用互补的研究专长。自动时序验证是数字电路物理实现的关键环节。时序验证确保电路的物理实现与设计人员的意图一致,尽管制造过程中引入了不确定性和限制。定时验证需要两个组件:数学基础和通过实现数学来实现验证过程的软件。这项工作的目标是为异步电路的定时验证开发这两个组件。该项目带来了来自两个不同学科的专业知识来承担这项工作:(i)异步电路设计和实现,以及(ii)异步分布式系统的理论。该项目将分布式系统文献中潜在因果关系的概念应用于异步电路的上下文。来自这两个学科的见解和技术的融合有望促进更快和节能电路的更好设计,以及改进验证和验证由它们构建的系统正确性的技术。
英文摘要
Enabled by research and development in advanced materials, nano-manufacturing, and digital computation, low-cost, high-performance, and low-power electronic components have yielded smart-phones, wireless connectivity, high-throughput networks, inexpensive data centers, to just name a few aspects of our modern digital economy. However, as the current technology approaches limits set by the laws of physics, gains in performance and power efficiency are no longer realizable through conventional techniques. It is critical that a diverse group of students be trained in unconventional approaches, so that they can take new ideas to practice as part of the semiconductor industry and continue the phenomenal growth of the past decades known as the Moore's law. Asynchronous circuits and systems design, to be pursued in this project, is one such unconventional approach being studied as a way to improve computational efficiency. The project also collaborates with the Binational Science Foundation (BSF) of Israel to leverage complementary research expertise.Automated timing validation is a critical component in physical realization of a digital circuit. Timing validation ensures that the physical implementation of the circuit is consistent with the intent of the designer, in spite of the uncertainties and constraints introduced by the manufacturing process. Two components are necessary for timing validation: a mathematical foundation, and software that realizes the validation process by implementing the mathematics. The goal of this effort is to develop these two components for the timing validation of asynchronous circuits. The project brings expertise from two different disciplines to bear on this effort: (i) asynchronous circuit design and implementation, and (ii) the theory of asynchronous distributed systems. The project adapts the concept of potential causality from the distributed systems literature to the context of asynchronous circuits. The fusion of insights and techniques from the two disciplines promises to facilitate better design of fast and energy-efficient circuits, as well as improving the techniques for validating and verifying the correctness of systems built from them.
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Summer School/Workshop on Asynchronous Logic: 2022
  • 批准号:
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