CCF-BSF:SHF: Small: Timing Validation for Asyncronous Circuits
CCF-BSF:SHF: Small: Timing Validation for Asyncronous Circuits
批准号:
1724992
负责人:
Rajit Manohar
金额:
$35.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2017
资助国家:
美国
项目状态:
已结题
起止时间:
2017-01-01 至 2020-07-31
中文摘要
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英文摘要
Enabled by research and development in advanced materials, nano-manufacturing, and digital computation, low-cost, high-performance, and low-power electronic components have yielded smart-phones, wireless connectivity, high-throughput networks, inexpensive data centers, to just name a few aspects of our modern digital economy. However, as the current technology approaches limits set by the laws of physics, gains in performance and power efficiency are no longer realizable through conventional techniques. It is critical that a diverse group of students be trained in unconventional approaches, so that they can take new ideas to practice as part of the semiconductor industry and continue the phenomenal growth of the past decades known as the Moore's law. Asynchronous circuits and systems design, to be pursued in this project, is one such unconventional approach being studied as a way to improve computational efficiency. The project also collaborates with the Binational Science Foundation (BSF) of Israel to leverage complementary research expertise.Automated timing validation is a critical component in physical realization of a digital circuit. Timing validation ensures that the physical implementation of the circuit is consistent with the intent of the designer, in spite of the uncertainties and constraints introduced by the manufacturing process. Two components are necessary for timing validation: a mathematical foundation, and software that realizes the validation process by implementing the mathematics. The goal of this effort is to develop these two components for the timing validation of asynchronous circuits. The project brings expertise from two different disciplines to bear on this effort: (i) asynchronous circuit design and implementation, and (ii) the theory of asynchronous distributed systems. The project adapts the concept of potential causality from the distributed systems literature to the context of asynchronous circuits. The fusion of insights and techniques from the two disciplines promises to facilitate better design of fast and energy-efficient circuits, as well as improving the techniques for validating and verifying the correctness of systems built from them.
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会议论文
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批准号:2227133
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项目类别:Standard Grant
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资助金额:$1.44万
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财政年份:2022
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负责人:Rajit Manohar
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依托单位:
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项目类别:Standard Grant
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资助金额:$7.28万
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负责人:Rajit Manohar
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依托单位:
CCF-BSF:SHF: Small: Timing Validation for Asyncronous Circuits
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项目类别:Standard Grant
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SHF:Small: Collaborative Research: CONTINUOUS-TIME DIGITAL COMPUTATION AND SIGNAL PROCESSING
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