SHF: Small: MultiSpot - Closing the power-delivery/heat-removal cycle for heterogeneous multiscale systems

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The semiconductor industry is poised to continue the historic Moore's law trend of doubling the level of integration every 18 months, even as the virtuous cycle benefits of Dennard scaling are quickly vanishing. Once devices no longer scale laterally, one way to continue to increase areal density is to use 3D integration. The main objective of the current project, called the MultiSpot project, is to provide fundamental solutions to the problem of 3D-IC power wall. These solutions could have a deep impact on the semiconductor industry, and thus the society as a whole by providing a path forward for Moore's law to take advantage of the third dimension. The project will also lead to new research infrastructure exemplified by the several high-impact architecture modeling tools for power and thermals previously developed by the PIs, such as HotSpot, HotLeakage VoltSpot, and ArchFP that have enabled extensive research at academic institutions and industry in the past. One approach is to provide very low impedance paths from the interior of the volume to the outside for power in addition to heat removal. A different dual use for microchannels is to modify their walls to create supercapacitors that can be useful to store extra charge to combat power brownouts or boost operations. An alternative method to address the power delivery volumetric/areal mismatch is voltage stacking, in which the different layers in a 3D-IC stack are electrically connected in series, instead of in parallel as in a conventional approach. MultiSpot proposes practical methods to complement and assist the implicit regulation of voltage stacking with the explicit regulation of multi-output switched-capacitor ladder networks. The project also considers cross-layer aspects, such as details of embedded capacitor technologies, the architectural implications of homogeneous vs. heterogeneous 3D-IC solutions, the modeling of power delivery and heat removal at the architecture level, and validation through modeling and simulations.