SBIR Phase II: A hardware FPGA implementation of H.265/HEVC low latency video encoder algorithms for professional applications

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The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to promote and improve the use of high quality video in products that the general public works with every day. From high resolution auto dashboard cameras, to low latency video streams from flying drones, to wireless laptop docking stations, to higher quality coverage of news and sporting events, to better and faster delivery of video over the Internet, every application requires the high quality, low latency, flexible, power efficient video encoders that will be developed in this project. The uses of video are increasing every day. Video instruction manuals are replacing printed instruction manuals. Video is replacing still images in on-line advertising, social media and billboards. It is predicted that over 90% of all Internet traffic will be video data in the next few years. Enabling all these applications requires the latest technology in video compression such as the techniques developed in this project.This Small Business Innovation Research (SBIR) Phase II project tackles the problem of creating a real time video encoder, using the latest H.265 compression technology, running in hardware on an FPGA (Field Programmable Gate Array). An FPGA is a type of chip on which the logic is configurable - it can be programmed to implement any function. It represents a mid-point between a dedicated integrated circuit, which is very expensive to develop, and can never be changed or enhanced once it is fabricated, and a pure software solution which is very flexible but requires bulky and power hungry equipment (i.e. computers) as an underlying platform. The research conducted under this grant will devise, test, and implement algorithms that are amenable to realization on an FPGA, that operate in real time, and that yield a high quality result in terms of the visual quality of the compressed video with respect to the number of bits used. The goal, at the conclusion of this research, is the demonstration of a functional HEVC/H.265 encoder running on an FPGA which has cost, flexibility, power and performance advantages over other encoders.