SBIR Phase II: A hardware FPGA implementation of H.265/HEVC low latency video encoder algorithms for professional applications

SBIR 第二阶段：适用于专业应用的 H.265/HEVC 低延迟视频编码器算法的硬件 FPGA 实现

• 批准号: 1632567
• 负责人: Adam Malamy
• 金额: $ 75万
• 依托单位: NGCodec Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-09-15 至 2019-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1632567&HistoricalAwards=false
• 关键词: SBIR; Phase; II; hardware; FPGA

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to promote and improve the use of high quality video in products that the general public works with every day. From high resolution auto dashboard cameras, to low latency video streams from flying drones, to wireless laptop docking stations, to higher quality coverage of news and sporting events, to better and faster delivery of video over the Internet, every application requires the high quality, low latency, flexible, power efficient video encoders that will be developed in this project. The uses of video are increasing every day. Video instruction manuals are replacing printed instruction manuals. Video is replacing still images in on-line advertising, social media and billboards. It is predicted that over 90% of all Internet traffic will be video data in the next few years. Enabling all these applications requires the latest technology in video compression such as the techniques developed in this project.This Small Business Innovation Research (SBIR) Phase II project tackles the problem of creating a real time video encoder, using the latest H.265 compression technology, running in hardware on an FPGA (Field Programmable Gate Array). An FPGA is a type of chip on which the logic is configurable - it can be programmed to implement any function. It represents a mid-point between a dedicated integrated circuit, which is very expensive to develop, and can never be changed or enhanced once it is fabricated, and a pure software solution which is very flexible but requires bulky and power hungry equipment (i.e. computers) as an underlying platform. The research conducted under this grant will devise, test, and implement algorithms that are amenable to realization on an FPGA, that operate in real time, and that yield a high quality result in terms of the visual quality of the compressed video with respect to the number of bits used. The goal, at the conclusion of this research, is the demonstration of a functional HEVC/H.265 encoder running on an FPGA which has cost, flexibility, power and performance advantages over other encoders.

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力是促进和改善普通公众每天使用的产品中高质量视频的使用。 从高分辨率的汽车仪表盘摄像头，到无人机的低延迟视频流，到无线笔记本电脑对接坞，到更高质量的新闻和体育赛事报道，再到通过互联网更好更快地交付视频，每个应用都需要高质量，低延迟，灵活，高能效的视频编码器，这些编码器将在本项目中开发。 视频的使用每天都在增加。 视频说明书正在取代印刷说明书。 视频正在取代在线广告、社交媒体和广告牌中的静止图像。 据预测，在未来几年内，超过90%的互联网流量将是视频数据。 要实现所有这些应用，需要视频压缩方面的最新技术，例如本项目中开发的技术。这个小型企业创新研究（SBIR）第二阶段项目解决了创建一个真实的时间视频编码器的问题，使用最新的H.265压缩技术，在FPGA（现场可编程门阵列）上的硬件上运行。 FPGA是一种可配置逻辑的芯片-它可以编程以实现任何功能。 它代表了专用集成电路和纯软件解决方案之间的中间点，专用集成电路的开发非常昂贵，并且一旦制造就永远不能改变或增强，纯软件解决方案非常灵活，但需要庞大且耗电的设备（即计算机）作为底层平台。 在此资助下进行的研究将设计，测试和实施算法，这些算法适合在FPGA上实现，在真实的时间内运行，并在压缩视频的视觉质量方面产生高质量的结果。 在本研究的最后，我们的目标是演示在FPGA上运行的功能性HEVC/H.265编码器，该编码器与其他编码器相比具有成本，灵活性，功耗和性能优势。