课题基金 / 基金详情

EAGER: Securing Integrated Circuits Through Realtime Hardware Trojan Detection

EAGER: Securing Integrated Circuits Through Realtime Hardware Trojan Detection
EAGER:通过实时硬件木马检测保护集成电路
批准号:
1648878
负责人:
Ioannis Savidis
金额:
$28.87万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2016
资助国家:
美国
项目状态:
已结题
起止时间:
2016-09-01 至 2019-08-31

项目摘要

项目成果

Ioannis Savidis的其他基金

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中文摘要
翻译
对集成电路(IC)的修改或外国知识产权的插入对美国主权构成严重威胁,因为IC被发现在许多消费电子设备中,包括电话,电脑和电视机。更重要的是,美国的许多商业和军事资产都依赖于IC来计算和管理关键基础设施,如银行、能源和国防系统。这项研究的主要目的是提高美国电子资产的安全性,确保放置在这些关键系统中的集成电路不包括损害运行这些复杂系统的集成电路完整性的功能或修改功能。这项研究将实现一种基于配电网络噪声的运行时检测方法,以有效地检测、定位、并从恶意电路修改中恢复。博弈论的一种新的应用将被用来优化配电网络上的电压传感器,以提高硬件木马的检测,因此,增加对手开发和实施攻击的成本。此外,该项目旨在开发两种技术来从硬件木马的激活中恢复:1)逻辑加密密钥操作,以及2)用于本地关闭IC部分的分段配电网络。还将开发自动插入检测硬件修改的电路的算法,从而导致半导体行业长期和广泛使用所提出的方法。总体而言,该项目有力地补充了正在进行的研究,检查硬件木马检测和对策。拟议研究的结果将产生新的电路技术和方法,以检测和消除由于对抗性修改而导致的电路异常,以及设计IP,以提高IC对电路攻击的鲁棒性。该项目的教育目标是开发用于检测、识别和定位硬件修改的安全IC设计实践。一门与拟议的研究及其应用有关的课程将开发并提供给研究生和高年级本科生。
英文摘要
Modifications to integrated circuits (ICs) or the insertion of foreign intellectual property pose a serious threat to U.S. sovereignty, as ICs are found in many consumer electronic devices, including phones, computers, and televisions. More importantly, many commercial and military U.S. assets rely on ICs for computation and management of critical infrastructure such as banking, energy, and defense systems. The primary impact of the proposed work is to improve the security of U.S. electronic assets by assuring that the integrated circuits placed in these critical systems do not include functions or modified functions that compromise the integrity of the ICs running these complex systems.The research will implement a run-time detection methodology based on the noise on the power distribution network to effectively detect, locate, and recover from malicious circuit modifications. A novel application of game theory will be utilized to optimally place voltage sensors on the power distribution network to enhance the detection of hardware Trojans, and therefore, increase the cost on the adversary to develop and implement an attack. In addition, the project aims to develop two techniques to recover from the activation of a hardware Trojan: 1) logic encryption key manipulation, and 2) a segmented power distribution network for locally powering off sections of an IC. Algorithms to automate the insertion of circuits that detect hardware modifications will also be developed, leading to long term and widespread use of the proposed methodologies by the semiconductor industry. Overall, the project strongly complements ongoing research examining hardware Trojan detection and countermeasures. The outcome of the proposed research will result in novel circuit techniques and methodologies to detect and neutralize circuit anomalies due to adversarial modifications, as well as design IP that improves the robustness of an IC against circuit attacks. The educational goal of the project is the development of secure IC design practices for the detection, identification, and localization of hardware modifications. A course related to the proposed research and its applications will be developed and offered to graduate and advanced undergraduate students.
期刊论文(7)
专著(0)
科研奖励(0)
会议论文
DOI: 10.1109/aspdac.2018.8297285
发表时间: 2018-01
期刊: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
影响因子: --
作者: [H. Sayadi;Divya Pathak;I. Savidis;H. Homayoun]
通讯作者: H. Sayadi;Divya Pathak;I. Savidis;H. Homayoun
Enhanced Circuit Security Through Hidden State Transitions
通过隐藏状态转换增强电路安全性
DOI: --
发表时间: 2018
期刊: Government Microcircuit Applications & Critical Technology Conference (GOMACTech
影响因子: --
作者: [Juretus, Kyle, Savidis, Ioannis]
通讯作者: Savidis, Ioannis
Physical gate based preamble obfuscation for securing wireless communication
基于物理门的前导码混淆,用于保护无线通信
DOI: 10.1109/iccnc.2017.7876142
发表时间: 2017
期刊: Networking and Communications (ICNC
影响因子: --
作者: [Chacko, James, Juretus, Kyle, Jacovic, Marko, Sahin, Cem, Kandasamy, Nagarajan, Savidis, Ioannis, Dandekar, Kapil]
通讯作者: Dandekar, Kapil
DOI: 10.1109/latw.2017.7906739
发表时间: 2017-03
期刊: 2017 18th IEEE Latin American Test Symposium (LATS)
影响因子: --
作者: [Vaibhav Venugopal Rao;I. Savidis]
通讯作者: Vaibhav Venugopal Rao;I. Savidis
7
    CAREER: Parameter Obfuscation: A Novel Methodology for the Protection of Analog Intellectual Property
    • 批准号:
      1751032
    • 项目类别:
      Continuing Grant
    • 资助金额:
      $50.37万
    • 财政年份:
      2018
    • 负责人:
      Ioannis Savidis
    • 依托单位:
    海外基金