CAREER: Parameter Obfuscation: A Novel Methodology for the Protection of Analog Intellectual Property

职业:参数混淆:保护模拟知识产权的新方法

基本信息

  • 批准号:
    1751032
  • 负责人:
  • 金额:
    $ 50.37万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2018
  • 资助国家:
    美国
  • 起止时间:
    2018-04-15 至 2025-03-31
  • 项目状态:
    未结题

项目摘要

Hardware security, specifically the protection of integrated circuit intellectual property (IP), has gained importance as adversaries have the financial and experiential means to reverse engineer and replicate competitors' IP. Significant research effort has been devoted to protecting digital circuits, but the protection of analog circuits from an adversary has largely been ignored. The focus of this work is to explore techniques to enhance the security of analog circuits from attacks such as reverse engineering and cloning, both of which can lead to IP theft. Analog parameter obfuscation is proposed as a means to protect analog circuits from adversarial theft. The large design space for analog parameter obfuscation, which includes biasing conditions, gains, bandwidths, noise figure, quality factors, center frequency, phase noise, and many more, provides a means to mask analog circuit functionality beyond the simple binary functional logic locking that has been developed for digital circuits. To enhance the security of analog circuits from reverse engineering, the proposed research includes 1) the development of novel parameter-based obfuscation techniques for analog circuits, 2) the development of algorithms and methodologies to select and prune analog circuit parameters (gain, biasing points, bandwidth, noise figure, quality factor, phase noise, etc.) best suited for obfuscation, 3) the development of initial metrics for the evaluation of parameter obfuscation techniques, and 4) the implementation of the obfuscation technique on a superheterodyne receiver for experimental verification and algorithm refinement. The fundamental outcome is to develop a systematic approach to analyze and obfuscate analog circuit parameters that are multi-dimensional and continuous by nature. The research results will be used to expose high school students to engineering topics through presentations and hands-on workshops. In addition, high school students will be mentored in research through an outreach program, initiated and led by the investigator, which pairs students with faculty mentors. The data generated from the project will be maintained online on a server at Drexel University (http://ice.ece.drexel.edu) - with the exception of publications, for which copyright is transferred to a professional organization (such as IEEE or ACM) and which maintain their own repository. At the completion of the project, all data and code will be released in the public domain and maintained in the repository for at least the required period set by agency and university guidelines.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
硬件安全,特别是集成电路知识产权(IP)的保护,已经变得越来越重要,因为对手有财务和经验手段来逆向工程和复制竞争对手的IP。大量的研究工作致力于保护数字电路,但模拟电路的保护在很大程度上被忽视了。 这项工作的重点是探索技术,以提高模拟电路的安全性,从攻击,如反向工程和克隆,这两个都可能导致IP盗窃。模拟参数混淆被提出作为一种手段,以保护模拟电路对抗盗窃。模拟参数混淆的大设计空间(包括偏置条件、增益、带宽、噪声系数、品质因数、中心频率、相位噪声等)提供了一种屏蔽模拟电路功能的手段,超越了为数字电路开发的简单二进制函数逻辑锁定。为了提高模拟电路逆向工程的安全性,本文提出的研究内容包括:1)开发新的基于参数的模拟电路混淆技术; 2)开发选择和修剪模拟电路参数(增益、偏置点、带宽、噪声系数、品质因数、相位噪声等)的算法和方法。最适合于混淆,3)开发用于评估参数混淆技术的初始度量,以及4)在超外差接收器上实现混淆技术以用于实验验证和算法改进。基本成果是开发一种系统的方法来分析和混淆模拟电路参数,是多维和连续的性质。 研究结果将用于通过演示和实践研讨会让高中生接触工程主题。此外,高中生将通过一个外展计划进行研究指导,该计划由研究人员发起和领导,该计划将学生与教师导师配对。该项目产生的数据将在线保存在德雷克塞尔大学的一个服务器上(http:ice.ece.drexel.edu),但出版物除外,其版权已转让给专业组织(如IEEE或ACM),并保持自己的存储库。在项目完成后,所有数据和代码将在公共领域发布,并至少在机构和大学指导方针规定的时间内在存储库中维护。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。

项目成果

期刊论文数量(9)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing
Mesh Based Obfuscation of Analog Circuit Properties
基于网格的模拟电路属性混淆
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
参数混淆模拟电路的性能和安全性分析
Security Vulnerabilities of Obfuscated Analog Circuits
混淆模拟电路的安全漏洞
A Power Side-Channel Attack on Flash ADC
对闪存 ADC 的电源侧通道攻击
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Ioannis Savidis其他文献

Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits
用于模拟电路布局后互连电容估计的边加权图神经网络
Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation
混合利用子图同构和关系图卷积网络进行模拟功能分组注释
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation
EDA-schema:用于数字设计自动化的图形数据模型架构和开放数据集
Transfer Learning of Arrival Time Prediction Models from a 65 nm to a 28 nm Process Node
从 65 nm 到 28 nm 工艺节点的到达时间预测模型的迁移学习
DNA: DC Nodal Analysis Attack for Analog Circuits
DNA:模拟电路的直流节点分析攻击

Ioannis Savidis的其他文献

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{{ truncateString('Ioannis Savidis', 18)}}的其他基金

EAGER: Securing Integrated Circuits Through Realtime Hardware Trojan Detection
EAGER:通过实时硬件木马检测保护集成电路
  • 批准号:
    1648878
  • 财政年份:
    2016
  • 资助金额:
    $ 50.37万
  • 项目类别:
    Standard Grant

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