Parallelization of the NC Channel for the Execution on Multicore Architectures

处理器技术的发展一直推动着数控技术的革新。随着计算能力的提高，NC通道可以通过更好的路径生成和执行算法以及附加功能进行扩展。然而，每核心性能的增长现在已经停止了。目前计算能力的提高只能通过提供多个核心来实现。但是今天已经有NC应用（例如，需要大的前瞻性的HSC应用），对于这些应用，单个核心的计算能力是不够的。然而，通过NC通道的功能单元在几个核心之间的细粒度分散来获得计算能力的额外增益现在是不可能的。为了向NC通道的资源匮乏部分提供足够的计算能力，需要超过当前程度的子组件的并行化。因此，本研究项目的目标是定义方法和策略，可用于并行化路径生成的NC通道的先前顺序的功能单元。

The developments in the area of processor technology have always promoted technological innovations in NC technology. Increasing computing power allowed the extension of the NC channel by better algorithms for path generation and execution and additional functionality. However, the gain in performance per core has come to a stop now. The current increase in computing power is only achieved by providing multiple cores. But already today there are NC applications (e.g. HSC applications that require a large look-ahead) for which the computing power of a single core is not sufficient. The additional gain of computing power by a fine-grained dispersion of functional units of the NC channel among several cores, however, is not possible nowadays. In order to provide adequate computing power to the resource-hungry parts of the NC channel, a parallelization of the subcomponents is needed which exceeds the current degree. The objective of this research project is therefore to define methods and strategies that can be used for parallelizing the previously sequential function units of the NC channel for path generation.