Parallelization of the NC Channel for the Execution on Multicore Architectures

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The developments in the area of processor technology have always promoted technological innovations in NC technology. Increasing computing power allowed the extension of the NC channel by better algorithms for path generation and execution and additional functionality. However, the gain in performance per core has come to a stop now. The current increase in computing power is only achieved by providing multiple cores. But already today there are NC applications (e.g. HSC applications that require a large look-ahead) for which the computing power of a single core is not sufficient. The additional gain of computing power by a fine-grained dispersion of functional units of the NC channel among several cores, however, is not possible nowadays. In order to provide adequate computing power to the resource-hungry parts of the NC channel, a parallelization of the subcomponents is needed which exceeds the current degree. The objective of this research project is therefore to define methods and strategies that can be used for parallelizing the previously sequential function units of the NC channel for path generation.