CIF:Small:High Performance Memories that Integrate Coding and Computer Architecture

第1部分：研究人员继续为计算机系统开发新的内存和存储技术，包括对固态驱动器中闪存的改进，以及尚未上市的新技术。这些技术提供了新的功能-包括更高的存储密度，或即使在没有电源的情况下也能保留数据的能力-但它们也带来了新的挑战，例如缩短了寿命，或者将数据写入内存的一部分可能会破坏其他部分的价值。从历史上看，通过对信息进行编码以恢复中断或丢失的数据，可以克服存储技术中的缺陷。然而，现有的技术不足以满足具有不同缺陷和不同使用模式的新兴存储技术。这个项目是信息论研究人员(研究如何为不同目的编码信息)和计算机体系结构研究人员(研究如何设计计算机系统，包括内存和存储)之间的合作。架构师将确定令人兴奋的技术及其带来的问题，信息理论家将开发新的信息编码方法来克服这些挑战。虽然编码方面的许多研究都是理论上的，与计算机系统的现实缺乏联系，但与专注于实现问题和成本的计算机架构师的合作将使编码工作奠定基础并增强其影响力。为了促进这一研究领域的更多跨学科工作，研究小组将在会议上提供半天的教程，包括在体系结构会议上的编码教程，以及在信息理论会议上的体系结构教程。调查人员将继续与本科生研究助理合作，包括S杜克大学普拉特工程学院暑期推广项目的学生。调查人员还将继续从代表性不足的人群中招聘女性研究助理；两名调查人员在这一领域都有广泛的跟踪记录，并致力于在计算研究社区中培养多样性。第2部分：拟议的研究计划寻求通过开发可在真实系统中实施的实用编码技术来提高现有和新兴存储技术--特别是闪存、3D DRAM和赛道内存--的寿命和容错能力。这些存储技术具有更高的存储密度，但受到有限寿命的特殊挑战，否则可能会限制它们在微体系结构中的潜力。历史上，存储器和存储的改进不仅归功于存储器技术本身的进步，还归功于设计存储器和存储系统的计算机架构师的创新，以及设计数据存储代码的编码理论家的创新。拟议的研究计划是由Pi Calderbank领导的编码理论小组和PI Sorin共同领导的计算机体系结构小组之间的合作。在他们的初步工作中，体系结构问题推动了新理论的发展，编码理论的进步推动了可以利用它们的新系统的发展。研究推动力可以按存储技术来分类，都包括具体的挑战以及更开放的研究方向：具体目标包括：1.开发新的赛道存储器编码解决方案，使用定界位来识别单个移位错误，并在识别后使用实际可实现的代码来纠正错误。引入跨多个赛道的编码(空间分集)以纠正多个移位错误。开发将计算机体系结构与编码理论创新相结合的虚拟多级闪存单元，并评估主机可见容量和使用寿命之间的权衡。开发新的编码解决方案，保护堆叠式DRAM设计不受位、行、库、通道、管芯和硅通孔故障的影响。制定堆叠设计中冗余如何与读/写延迟、带宽要求和能耗进行权衡的基本限制。

Part 1:Researchers continue to develope new memory and storage technologies for computer systems, including improvements to Flash memory in solid-state drives, as well as novel technologies that have not yet reached the market. These technologies offer new features---including greater storage density, or the ability to retain their data even without power---yet they also introduce new challenges, such as reduced lifetimes or the possibility that writing data into one part of the memory could disrupt values in other parts. Historically, imperfections in memory technologies have been overcome by encoding the information such that disrupted or lost data can be recovered. However, existing techniques do not suffice for the newly emerging memory technologies that have different imperfections and divergent usage models. This project is a collaboration between researchers in information theory (who study how to encode information for different purposes) and researchers in computer architecture (who study how to design computer systems, including memory and storage). The architects will identify exciting technologies and the problems they introduce, and the information theorists will develop new ways of encoding information to overcome these challenges. Whereas much research in coding is theoretical and lacks connection to the reality of computer systems, the collaboration with computer architects---who focus on implementation issues and costs---will ground the coding work and enhance its impact.To foster more interdisciplinary work in this research area, the research team will present half-day tutorials at conferences, including a coding tutorial at an architecture conference, and an architecture tutorial at an information theory conference. The investigators will continue to work with undergraduate research assistants, including students from an established summer outreach program at Duke?s Pratt School of Engineering. The investigators will also continue to recruit female research assistants alongside research assistants from under-represented populations; both investigators have extensive track records in this area and are committed to cultivating diversity in the computing research community.Part 2:The proposed research program seeks to improve the lifetime and fault tolerance of existing and emerging storage technologies---specifically Flash, 3D DRAM, and racetrack memory---by developing practical coding techniques that can be implemented in real-world systems. These storage technologies feature increased storage density, yet suffer the particular challenge of limited lifetime, that might otherwise limit their potential in microarchitectures.Historically, improvements in memory and storage have been due not only to advances in the memory technologies themselves, but also to innovations by computer architects who design memory and storage systems and by coding theorists who devise codes for data storage. The proposed research program is a collaboration between a coding theory group led by PI Calderbank and a computer architecture group led by co-PI Sorin. In their preliminary work, architecture problems have driven development of new theory, and advances in coding theory have driven development of new systems that can take advantage of them.The research thrusts can be classified by the memory technology, and all include specific challenges as well as more open-ended research directions: Specific objectives include1. Development of new coding solutions for racetrack memory that employ delimiter bits to identify single shift errors and practically implementable codes to correct the error, once identified. Introduction of coding across multiple racetracks (spatial diversity) to correct multiple shift errors.2. Development of virtual multilevel Flash cells that connect computer architecture with coding theoretic innovations, and evaluation of the tradeoff between host-visible capacity and lifetime.3. Development of new coding solutions that protect stacked DRAM designs from failures in bits, rows, banks, channels, dies and through silicon vias. Development of fundamental limits on how redundancy trades off against read/write latency, bandwidth requirements, and energy consumption in stacked designs.