CIF:Small:High Performance Memories that Integrate Coding and Computer Architecture

CIF：Small：集成编码和计算机架构的高性能存储器

• 批准号: 1717602
• 负责人: Arthur Calderbank
• 金额: $ 47万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2020-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1717602&HistoricalAwards=false
• 关键词: CIF; Small; Performance; Memories; Integrate

Part 1:Researchers continue to develope new memory and storage technologies for computer systems, including improvements to Flash memory in solid-state drives, as well as novel technologies that have not yet reached the market. These technologies offer new features---including greater storage density, or the ability to retain their data even without power---yet they also introduce new challenges, such as reduced lifetimes or the possibility that writing data into one part of the memory could disrupt values in other parts. Historically, imperfections in memory technologies have been overcome by encoding the information such that disrupted or lost data can be recovered. However, existing techniques do not suffice for the newly emerging memory technologies that have different imperfections and divergent usage models. This project is a collaboration between researchers in information theory (who study how to encode information for different purposes) and researchers in computer architecture (who study how to design computer systems, including memory and storage). The architects will identify exciting technologies and the problems they introduce, and the information theorists will develop new ways of encoding information to overcome these challenges. Whereas much research in coding is theoretical and lacks connection to the reality of computer systems, the collaboration with computer architects---who focus on implementation issues and costs---will ground the coding work and enhance its impact.To foster more interdisciplinary work in this research area, the research team will present half-day tutorials at conferences, including a coding tutorial at an architecture conference, and an architecture tutorial at an information theory conference. The investigators will continue to work with undergraduate research assistants, including students from an established summer outreach program at Duke?s Pratt School of Engineering. The investigators will also continue to recruit female research assistants alongside research assistants from under-represented populations; both investigators have extensive track records in this area and are committed to cultivating diversity in the computing research community.Part 2:The proposed research program seeks to improve the lifetime and fault tolerance of existing and emerging storage technologies---specifically Flash, 3D DRAM, and racetrack memory---by developing practical coding techniques that can be implemented in real-world systems. These storage technologies feature increased storage density, yet suffer the particular challenge of limited lifetime, that might otherwise limit their potential in microarchitectures.Historically, improvements in memory and storage have been due not only to advances in the memory technologies themselves, but also to innovations by computer architects who design memory and storage systems and by coding theorists who devise codes for data storage. The proposed research program is a collaboration between a coding theory group led by PI Calderbank and a computer architecture group led by co-PI Sorin. In their preliminary work, architecture problems have driven development of new theory, and advances in coding theory have driven development of new systems that can take advantage of them.The research thrusts can be classified by the memory technology, and all include specific challenges as well as more open-ended research directions: Specific objectives include1. Development of new coding solutions for racetrack memory that employ delimiter bits to identify single shift errors and practically implementable codes to correct the error, once identified. Introduction of coding across multiple racetracks (spatial diversity) to correct multiple shift errors.2. Development of virtual multilevel Flash cells that connect computer architecture with coding theoretic innovations, and evaluation of the tradeoff between host-visible capacity and lifetime.3. Development of new coding solutions that protect stacked DRAM designs from failures in bits, rows, banks, channels, dies and through silicon vias. Development of fundamental limits on how redundancy trades off against read/write latency, bandwidth requirements, and energy consumption in stacked designs.

第1部分：研究人员继续为计算机系统开发新的内存和存储技术，包括改进固态驱动器中的闪存，以及尚未进入市场的新技术。 这些技术提供了新的功能-包括更大的存储密度，或者即使在没有电源的情况下也能保留数据-但它们也带来了新的挑战，例如缩短了使用寿命，或者将数据写入内存的一部分可能会破坏其他部分的值。历史上，存储器技术的缺陷已经通过对信息进行编码来克服，使得可以恢复中断或丢失的数据。 然而，现有的技术不足以为新兴的内存技术，有不同的缺陷和不同的使用模式。 该项目是信息理论研究人员（研究如何为不同目的编码信息）和计算机体系结构研究人员（研究如何设计计算机系统，包括内存和存储）之间的合作。 架构师将确定令人兴奋的技术和它们引入的问题，信息理论家将开发编码信息的新方法来克服这些挑战。 尽管编码方面的许多研究都是理论性的，缺乏与计算机系统现实的联系，但与计算机架构师的合作--他们专注于实现问题和成本--将为编码工作奠定基础并增强其影响力。为了促进这一研究领域的更多跨学科工作，研究团队将在会议上提供半天的教程，包括在架构会议上的编码教程，和信息论会议上的架构教程研究人员将继续与本科生研究助理合作，包括来自杜克大学一个既定暑期拓展项目的学生。普拉特工程学院。研究人员还将继续招募女性研究助理和来自代表性不足人群的研究助理;两位研究人员在这一领域有着广泛的记录，并致力于培养计算研究社区的多样性。第二部分：拟议的研究计划旨在通过开发可在现实世界系统中实现的实用编码技术，提高现有和新兴存储技术的寿命和容错能力，特别是Flash，3D DRAM和赛道存储器。这些存储技术的特点是增加了存储密度，但也面临着寿命有限的特殊挑战，这可能会限制它们在微架构中的潜力。历史上，内存和存储的改进不仅归功于内存技术本身的进步，还归功于设计内存和存储系统的计算机架构师和设计数据存储代码的编码理论家的创新。拟议的研究计划是由PI Calderbank领导的编码理论小组和由共同PI Sorin领导的计算机架构小组之间的合作。在他们的前期工作中，架构问题推动了新理论的发展，编码理论的进步推动了可以利用它们的新系统的发展。研究重点可以按存储技术分类，都包括特定的挑战以及更开放的研究方向：具体目标包括1.为赛道存储器开发新的编码解决方案，采用双比特来识别单移位错误，并在识别后使用实际可实现的代码来纠正错误。引入跨多个跑道的编码（空间分集）来纠正多个移位错误。开发虚拟多级Flash单元，将计算机体系结构与编码理论创新联系起来，并评估主机可见容量和寿命之间的权衡.开发新的编码解决方案，保护堆叠DRAM设计免受位、行、库、通道、管芯和硅通孔故障的影响。在堆叠设计中，冗余如何权衡读/写延迟、带宽要求和能耗的基本限制。

项目成果

GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors

GreenFlag：保护 3D 赛道内存免受移位错误的影响

• DOI: 10.1109/dsn.2019.00016
• 发表时间: 2019
• 期刊: 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019
• 作者: Mappouras, Georgios;Vahid, Alireza;Calderbank, Robert;Sorin, Daniel J.
• 通讯作者: Sorin, Daniel J.

Topology-Aware Cooperative Data Protection in Blockchain-Based Decentralized Storage Networks

• DOI: 10.1109/isit44484.2020.9174443
• 发表时间: 2020-01
• 期刊: 2020 IEEE International Symposium on Information Theory (ISIT)
• 作者: Siyi Yang;Ahmed Hareedy;A. Calderbank;L. Dolecek

Increasing the Lifetime of Flash Memories Using Multi-Dimensional Graph-Based Codes

• DOI: 10.1109/itw44776.2019.8989395
• 发表时间: 2019-08
• 期刊: 2019 IEEE Information Theory Workshop (ITW)
• 作者: Ahmed Hareedy;Rohith Kuditipudi;Robert Calderbank

Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice

• DOI: 10.1109/tcad.2018.2857059
• 发表时间: 2018-11-01
• 期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
• 影响因子: 2.9
• 作者: Mappouras, Georgios;Vahid, Alireza;Sorin, Daniel J.
• 通讯作者: Sorin, Daniel J.

Q-ary Asymmetric LOCO Codes: Constrained Codes Supporting Flash Evolution

Q 元非对称 LOCO 代码：支持闪存演进的约束代码

• DOI: 10.1109/isit44484.2020.9174176
• 发表时间: 2020
• 期刊: IEEE International Symposium on Information Theory (ISIT 2020
• 作者: Hareedy, Ahmed;Dabak, Beyza;Calderbank, Robert
• 通讯作者: Calderbank, Robert