CAPA: Collaborative Research: ARION: Taming Heterogeneity with DSLs, Approximation, and Synthesis

点击翻译按钮获取中文摘要

Specialization and the arrival of new technologies are key forces motivating heterogeneous systems. Heterogeneity is already in use widely, with public clouds offering instances that are heterogeneous in both compute capabilities and storage. This project identifies the following forces that will make systems heterogeneous beyond just compute and storage, complicating programming and compilation beyond the challenges that we face today. This project develops Arion, a system for compiling programs onto heterogeneous platforms based on several unifying ideas. The Arion system will be evaluated on practically relevant workloads ranging from computer vision and virtual reality, to graph computations, machine learning and stream processing. The investigators will work with partners in industry to transfer research results to products, and the tools and software developed by this project will be released as open source.The research in this project relies on four unifying ideas. The first thrust explores schedules and type systems separate a program's specification from its implementation strategy, enabling performance portability because one can select, without changing the program, its parallelism, locality, and hardware mapping. The second thrust uses domain-specific languages to describe not only programs but also artifacts used during compilation, such as schedules, resource-, and memory consistency models. This allows automatic synthesis of these artifacts. The third thrust uses resource models to bring scheduling and synthesis to large programs because the target program need not be scheduled or synthesized all at once. Instead, the compiler makes high-level decisions by estimating performance using a model before committing to low-level decisions. Finally, the investigators will use formal methods to lift programs into, and verify and synthesize programs in our DSLs, providing a high degree of automation. The verifiers and synthesizers are automatically generated from descriptions of DSLs.