CAPA: Collaborative Research: A Multi-Paradigm Programming Infrastructure for Heterogeneous Architectures

广泛使用硬件加速器（如fpga和gpu）的异构计算已经显示出巨大的希望，可以为广泛的应用程序带来数量级的计算效率提高。然而，这种异构平台很难编程，特别是使用fpga，限制了它们的使用，只有一小部分具有专门硬件知识的程序员。这项研究的智力优势在于为异构架构开发了一种高效的多范式编程基础设施，该基础设施集成了方便的异构编程模型、高级领域特定语言的自动编译、新颖的运行时和调试支持。该项目更广泛的意义和重要性在于，将最新的研究成果引入多个研究生和本科生的课程和主要会议的教程中，目的是培养新一代多样化的学生和专业人员使用异构编程模型。这些程序员将能够将开发的基础设施有效地应用于我们社会中许多重要的计算密集型应用，以进一步推动数字革命。具体而言，该项目有四个创新研究组成部分：(1)一种新的编程模型，称为HeteroCL，它可以在一个单一的统一程序中对异构系统进行编程；(2)一种可重用的方法，可以有效地将高级dsl转换为HeteroCL；(3)一种高效的运行时系统，它支持HeteroCL编程模型和高级dsl，具有在多个计算层次上动态和智能地将工作负载协同调度到cpu和加速器的独特能力。(4)用于仪表和性能监控的新型FPGA性能调试工具。

Heterogeneous computing with extensive use of hardware accelerators, such as FPGAs and GPUs, has shown great promise to bring in orders of magnitude improvement in computing efficiency for a wide range of applications. However, such heterogeneous platforms are difficult to program, especially with FPGAs, limiting their use to only a small subset of programmers with specialized hardware knowledge. The intellectual merits of this research are to develop a highly productive multi-paradigm programming infrastructure for heterogeneous architectures that integrates convenient heterogeneous programming models, automated compilation for high-level domain-specific languages, novel runtime, and debugging support. The project's broader significance and importance are to introduce the latest research into multiple graduate and undergraduate courses and tutorials at major conferences, with the goal of training a new generation of diverse students and professionals to use heterogeneous programming models. These programmers will be able to apply the developed infrastructure effectively to many important compute-intensive applications in our society to further the digital revolution. Specifically, the project has four innovative research components: (1) a new programming model, named HeteroCL, that enables programming of heterogeneous systems in a single unified program, (2) a reusable methodology to efficiently transform high-level DSLs to HeteroCL, (3) an efficient runtime system that support the HeteroCL programming model and high-level DSLs, with unique capability of dynamic and intelligent co-scheduling of workloads to CPUs and accelerators at multiple levels of computing hierarchy, and (4) novel FPGA performance debugging tools for instrumentation and performance monitoring.