CAPA: Collaborative Research: A Multi-Paradigm Programming Infrastructure for Heterogeneous Architectures

随着硬件加速器的广泛使用，如现场可编程门阵列和图形处理器的广泛使用，异质计算已经显示出在广泛的应用中带来数量级的计算效率提高的巨大希望。然而，这种不同的平台很难编程，特别是在使用现场可编程门阵列的情况下，它们的使用仅限于具有专门硬件知识的程序员的一小部分。这项研究的智力价值在于为异类体系结构开发了一个高效的多范例编程基础设施，该基础设施集成了方便的异类编程模型、高级领域特定语言的自动编译、新颖的运行时和调试支持。该项目的更广泛的意义和重要性是在主要会议上将最新研究引入多个研究生和本科生课程和教程，目标是培训新一代不同的学生和专业人员使用不同的编程模型。这些程序员将能够将开发的基础设施有效地应用于我们社会中许多重要的计算密集型应用程序，以推动数字革命。具体地说，该项目有四个创新的研究组成部分：(1)一个新的编程模型，称为HeteroCL，允许在单一的统一程序中对不同的系统进行编程；(2)可重用的方法，高效地将高级DSL转换为HeteroCL；(3)高效的运行时系统，支持HeteroCL编程模型和高级DSL，具有独特的能力，动态和智能地共同调度工作负载到多个计算层次结构的CPU和加速器；(4)新的用于插装和性能监控的FPGA性能调试工具。

Heterogeneous computing with extensive use of hardware accelerators, such as FPGAs and GPUs, has shown great promise to bring in orders of magnitude improvement in computing efficiency for a wide range of applications. However, such heterogeneous platforms are difficult to program, especially with FPGAs, limiting their use to only a small subset of programmers with specialized hardware knowledge. The intellectual merits of this research are to develop a highly productive multi-paradigm programming infrastructure for heterogeneous architectures that integrates convenient heterogeneous programming models, automated compilation for high-level domain-specific languages, novel runtime, and debugging support. The project's broader significance and importance are to introduce the latest research into multiple graduate and undergraduate courses and tutorials at major conferences, with the goal of training a new generation of diverse students and professionals to use heterogeneous programming models. These programmers will be able to apply the developed infrastructure effectively to many important compute-intensive applications in our society to further the digital revolution. Specifically, the project has four innovative research components: (1) a new programming model, named HeteroCL, that enables programming of heterogeneous systems in a single unified program, (2) a reusable methodology to efficiently transform high-level DSLs to HeteroCL, (3) an efficient runtime system that support the HeteroCL programming model and high-level DSLs, with unique capability of dynamic and intelligent co-scheduling of workloads to CPUs and accelerators at multiple levels of computing hierarchy, and (4) novel FPGA performance debugging tools for instrumentation and performance monitoring.