SBIR Phase I: High Fidelity EUV PhotoMasks

这个小型企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是通过制造长度为7纳米或更小的电子系统基本单元集成电路来推动下一代先进的计算能力和性能。今天好吗?每个中央处理器（cpu）包含72亿个芯片，每年生产超过1.2万亿颗芯片以满足计算需求。下一代技术有望通过传统计算和潜在的神经形态范式实现人工智能和机器学习，将自动驾驶汽车和智能建筑等变革性应用变为现实。摩尔?随着技术进步的步伐不断加快，芯片制造商将部署新的EUV（极紫外线）光刻工具，使用13.5 nm的光在硅片上设计集成电路或芯片架构，以实现下一代技术。芯片制造商努力在2019年实现EUV技术的准备。随着人口超过70亿，全球对下一代电子产品的需求将永远增长。然而，全球电子产品供应不断面临着降低成本和提供超越摩尔？年代法律。拟议的项目解决了在7nm节点上光刻工具及其组件的大批量生产的挑战。例如，EUV光掩模，一种高级商品组件，图案和复制集成电路设计到硅片上。目前的EUV光掩膜的产率约为60%，并且在其结构制造过程中存在缺陷。在操作使用过程中，掩模受到了EUV等离子体光源产生的碎片的破坏，这些碎片植入掩模并不可避免地在晶圆中复制，破坏了集成芯片图案。在大批量生产中，这些问题体现在晶圆产量、掩模的可重复使用性上，并推动了对高成本实时检测和计量的需求。提出了一种新的EUV光掩模，具有更强的缺陷鲁棒性、更高的制造成品率、更高的操作可重用性和更长的使用寿命。该项目的目标是评估用于EUV掩模设计的新集成架构，开发更高良率的制造工艺并表征EUV性能。更坚固的光罩减少了原位计量和检查所需的资本支出，并最终降低了下一代电子产品的成本。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to drive the next generation of advanced computing power and performance, by manufacturing integrated circuits, the fundamental units of electronic systems, at length scales of 7 nm and smaller. Today?s central processing units (CPUs) each contain 7.2 Bn chips and over 1.2 sextillion chips are manufactured per year to meet computing demands. Next generation technology is expected to enable artificial intelligence and machine learning through both conventional computing and potentially neuromorphic paradigms, bringing to reality transformative applications such as self-driving cars and smart buildings. As Moore?s law continues to set the pace of technological advancement, chipmakers will deploy new EUV (Extreme Ultraviolet) lithography tools, using light of 13.5 nm to pattern integrated circuits or chip architecture into silicon wafers, for the next three generations of technology. Chipmakers strive to bring about the readiness of EUV technology in 2019. The global demand for next generation electronics is forever increasing as the population grows above 7 Bn. However, the global supply of electronics constantly faces challenges to reduce costs and deliver technology beyond Moore?s Law.The proposed project addresses the challenges related to high volume manufacturing at the 7 nm node for lithography tools and its components. For example, an EUV photomask, a high commodity component, patterns and replicates integrated circuit design into silicon wafers. Current EUV photomasks have a sub-optimal manufacturing yield of ~60% and suffer from defectivity which arises during fabrication of its architecture. During operational use the photomask sustains damage from the debris generated by the EUV plasma light source that implants in the mask and inevitably replicates in the wafer, destroying the integrated chip pattern. In high volume manufacturing, these issues manifest in the wafer yield, the reusability of a mask, and drive the need for high cost real-time inspection and metrology. A new EUV photomask which promises greater robustness to defects, a higher manufacturing yield, more reusability of masks in operations and a longer lifetime is presented. The goals of the project are to evaluate new integrated architecture for the EUV mask design, develop a higher yield fabrication process and characterize the EUV performance. More robust photomasks reduce the capital outlay required for in-situ metrology and inspection and ultimately bring down the cost of next generation electronics.