SHF:Medium:Collaborative Research:Fine-Grain Multithreading through Hardware/Software Co-Design

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The supercomputing landscape has fundamentally changed in the past fifteen years. Chips have evolved from single-thread, single-core to multi-threaded, many-core chips. Even mainstream high-performance chips offer close to 100 hardware threads. At the same time, accelerators, featuring hundreds or even thousands of hardware threads, have allowed scientists to obtain major performance speedups for certain classes of scientific kernels, thanks to their inherent massively parallel nature. From the software side, programming languages can provide a way to create various types of parallelism, from traditional data-parallel constructs to fine-grain, data-driven ones: directives have been added to leverage instruction-level parallelism (ILP), thus allowing the programmer to identify when the code is vectorizable; accelerator-friendly directives allow code to execute on GPUs or the Intel Xeon Phi; finally, new keywords enable the programmer to express task-dependent parallelism. In order to evaluate the hardware-software trade-offs, the investigators plan to design and develop an abstract machine model for scalable parallel and distributed computing, designing and implementing hardware-assisted mechanisms to realize it. Through a broad dissemination of the research findings and tools to the community via conferences and publications, seminars, and a dedicated website, this research has the potential to foster new directions in holistic and comprehensive solutions important to humanity. In addition, the investigators have recently co-founded a Special Technical Community (Parallel Models & Systems) of the IEEE Computer Society with the specific purpose of fostering research and education in the domain across US and the world.This project seeks to develop an asynchronous fine-grain event-driven program execution model, Codelet Abstract Machine model (CAM), for thread management in parallel and distributed systems. The research tasks include three major extensions to a dataflow codelet model, implementing CAM by a hardware/software co-design approach and evaluating it using a set of benchmarks and applications. The proposed FPGA-based prototype is built in combination with general-purpose multicore chips and compiler and runtime system currently under development are designed be part of the system to allow high-level programmers to exploit the resulting system targeted to applications ranging from traditional HPC, parallel graph processing, as well as big data frameworks.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.