SHF: Compute Caches: Opportunistic Parallelism in General Purpose Processors at Extreme Scale

SHF：计算缓存：超大规模通用处理器中的机会并行

• 批准号: 1763918
• 负责人: Reetuparna Das
• 金额: $ 30万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-10-01 至 2021-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1763918&HistoricalAwards=false
• 关键词: SHF; Compute; Caches; Opportunistic; Parallelism

Computer designers have traditionally separated the role of storage and compute units. Memories and caches stored data. Processors' logic units computed them. It is not obvious that this separation is needed. A human brain does not separate the two so distinctly. This project addresses this fundamental question regarding the role of caches. Caches are used in almost all modern processors. They occupy a large fraction (over 70%) of the computer chip area. Latest Intel's server class Xeon processor, for instance, devotes several tens of megabytes just for its last-level cache. By avoiding movement of data in and out of memory arrays, this project will demonstrate the efficiency of compute caches, across a broad range of data-intensive applications that span several domains: cognitive computing, data analytics, security and graphs, and save vast amounts of energy spent in shuffling data between compute and memory units in modern computing systems. This project will develop novel SRAM array designs for supporting a rich set of operation types and address various architectural challenges that arise in integrating highly parallel compute caches with a general-purpose host processor. Until today, caches have served only as an intermediate low-latency storage unit. This project directly challenges this conventional design, and imposes a dual responsibility on caches: store and compute data. The key advantage of this approach is that it allows data stored across hundreds of memory arrays in caches to be operated on concurrently. The end result is that memory arrays morph into massive vector compute units that are potentially one to two orders of magnitude wider than a modern graphics processors (GPUs) vector units. This project considers vertically integrated solutions that cut across the computing stack: circuits, architecture, compilers, to applications.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

传统上，计算机设计者将存储单元和计算单元的角色分开。存储和缓存存储的数据。处理器的逻辑单元计算它们。显然，这种分离是不是必要的。人类的大脑不会如此明显地区分这两者。这个项目解决了关于缓存角色的这个基本问题。几乎所有现代处理器都使用缓存。它们占据了计算机芯片面积的很大一部分(超过70%)。例如，最新的英特尔服务器级至强处理器仅为其末级高速缓存就投入了数十兆字节。通过避免将数据移入和移出内存阵列，该项目将展示计算缓存在认知计算、数据分析、安全和图表等多个领域的广泛数据密集型应用程序中的效率，并节省在现代计算系统的计算和存储单元之间洗牌数据所花费的大量能源。该项目将开发新的SRAM阵列设计，以支持丰富的操作类型集，并解决在将高度并行的计算高速缓存与通用主机处理器集成时出现的各种架构挑战。到目前为止，缓存只是充当中间的低延迟存储单元。该项目直接挑战了这一传统设计，并对缓存施加了双重责任：存储和计算数据。这种方法的主要优点是，它允许同时操作存储在高速缓存中的数百个内存阵列中的数据。最终的结果是，存储器阵列变形为大规模的矢量计算单元，这些单元可能比现代图形处理器(GPU)的矢量单元宽一到两个数量级。该项目考虑跨越计算堆栈的垂直集成解决方案：电路、体系结构、编译器和应用程序。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs

• DOI: 10.1109/fccm51124.2021.00018
• 发表时间: 2021-05
• 期刊: 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
• 作者: Xiaowei Wang;Vidushi Goyal;Jiecao Yu;V. Bertacco;Andrew Boutros;Eriko Nurvitadhi;C. Augustine;R. Iyer;R. Das

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

• DOI: 10.1109/jssc.2019.2939682
• 发表时间: 2020-01
• 期刊: IEEE Journal of Solid-State Circuits
• 影响因子: 5.4
• 作者: Jingcheng Wang;Xiaowei Wang;Charles Eckert;Arun K. Subramaniyan;R. Das;D. Blaauw;D. Sylvester

Duality Cache for Data Parallel Acceleration

• DOI: 10.1145/3307650.3322257
• 发表时间: 2019-06
• 期刊: 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Daichi Fujiki;S. Mahlke;R. Das