SHF: Compute Caches: Opportunistic Parallelism in General Purpose Processors at Extreme Scale

计算机设计师传统上将存储单元和计算单元的角色分开。记忆和缓存存储的数据。处理器的逻辑单元计算它们。显然，这种分离是不必要的。人类的大脑并不能如此明显地将两者分开。这个项目解决了这个关于缓存作用的基本问题。几乎所有现代处理器都使用高速缓存。它们占据了计算机芯片面积的很大一部分（超过70%）。例如，最新的英特尔服务器级至强处理器仅为其最后一级缓存贡献了几十兆字节。通过避免数据进出内存阵列的移动，该项目将展示计算缓存的效率，跨越跨越多个领域的广泛数据密集型应用：认知计算，数据分析，安全和图形，并节省大量的能量在现代计算系统中的计算和内存单元之间洗牌数据。该项目将开发新颖的SRAM阵列设计，以支持丰富的操作类型，并解决在将高度并行计算缓存与通用主机处理器集成时出现的各种架构挑战。到目前为止，高速缓存仅用作中间低延迟存储单元。这个项目直接挑战了这种传统的设计，并对缓存施加了双重责任：存储和计算数据。这种方法的主要优点是，它允许同时操作存储在高速缓存中的数百个存储器阵列中的数据。最终的结果是，存储器阵列演变成大规模的向量计算单元，其可能比现代图形处理器（GPU）向量单元宽一到两个数量级。该项目考虑跨越计算堆栈的垂直集成解决方案：电路，架构，编译器，应用程序。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Computer designers have traditionally separated the role of storage and compute units. Memories and caches stored data. Processors' logic units computed them. It is not obvious that this separation is needed. A human brain does not separate the two so distinctly. This project addresses this fundamental question regarding the role of caches. Caches are used in almost all modern processors. They occupy a large fraction (over 70%) of the computer chip area. Latest Intel's server class Xeon processor, for instance, devotes several tens of megabytes just for its last-level cache. By avoiding movement of data in and out of memory arrays, this project will demonstrate the efficiency of compute caches, across a broad range of data-intensive applications that span several domains: cognitive computing, data analytics, security and graphs, and save vast amounts of energy spent in shuffling data between compute and memory units in modern computing systems. This project will develop novel SRAM array designs for supporting a rich set of operation types and address various architectural challenges that arise in integrating highly parallel compute caches with a general-purpose host processor. Until today, caches have served only as an intermediate low-latency storage unit. This project directly challenges this conventional design, and imposes a dual responsibility on caches: store and compute data. The key advantage of this approach is that it allows data stored across hundreds of memory arrays in caches to be operated on concurrently. The end result is that memory arrays morph into massive vector compute units that are potentially one to two orders of magnitude wider than a modern graphics processors (GPUs) vector units. This project considers vertically integrated solutions that cut across the computing stack: circuits, architecture, compilers, to applications.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.