EAGER:Scaling On-Chip Interconnects for Exascale Systems

EAGER：扩展百亿亿级系统的片上互连

• 批准号: 1256203
• 负责人: Reetuparna Das
• 金额: $ 8.99万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-15 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1256203&HistoricalAwards=false
• 关键词: EAGER; Scaling; Chip; Interconnects; Exascale

This research aims to overcome the extreme challenges that need to be solved to realize a 1000-core (kilocore) processor. Processors with tens of cores are already in commercial products today. A kilocore processor could take us into the era of Server-on-Chip and Supercomputer-on-Chip. On-chip network is the medium through which two nodes in a processor can communicate, and therefore constitutes the backbone of a kilocore processor. Unfortunately, current on-chip network solutions are inadequate as they do not scale in terms of both power and performance beyond a few tens of cores. To reach the ambitious design goal of 1000+ cores with realistic power budgets, the interconnect technology needs to be at least 15 times more power efficient while providing at least the same level of throughput-per-core as today. This project investigates three interrelated solutions to meet the above challenge in an evolutionary manner: (1) Developing a low-power and energy-proportional interconnect architecture that employs a larger number of narrower networks, (2) Using high-radix Swizzle-Switches as the building blocks for interconnecting the multiple networks, and (3) Re-designing network architecture with multiple networks and Swizzle-Switches using 3D integration with Through-Silicon-Vias to achieve scalability beyond 1000 cores. This project will demonstrate the feasibility of kilocore processors. If such processors can be built, they could have a tremendous impact on future exascale systems such as cloud computing servers and HPC systems that have many applications including drug discovery, defense, information analysis, and social networking.

本研究旨在克服实现1000核（千核）处理器所需解决的极端挑战。具有数十个核心的处理器今天已经在商业产品中。千核处理器可以将我们带入片上服务器和片上超级计算机的时代。片上网络是处理器中两个节点之间进行通信的媒介，是千核处理器的骨干网络。不幸的是，当前的片上网络解决方案还不够，因为它们在功率和性能方面的扩展不能超过几十个核心。为了实现1000多个内核的宏伟设计目标，并提供现实的功耗预算，互连技术需要至少提高15倍的能效，同时提供至少与当前相同的每内核吞吐量水平。本项目研究三个相互关联的解决方案，以渐进的方式应对上述挑战：（1）开发一种低功率和能量比例的互连架构，其采用大量较窄的网络，（2）使用高基数Swizzle-Switch作为用于互连多个网络的构建块，以及（3）重新设计具有多个网络和Swizzle-Switch的网络架构，使用3D集成与硅通孔，以实现超过1000个核心的可扩展性。该项目将展示千核处理器的可行性。如果这种处理器能够被制造出来，它们可能会对未来的艾级系统产生巨大的影响，例如云计算服务器和HPC系统，这些系统具有许多应用，包括药物发现，国防，信息分析和社交网络。