EAGER:Scaling On-Chip Interconnects for Exascale Systems
EAGER:Scaling On-Chip Interconnects for Exascale Systems
批准号:
1256203
负责人:
Reetuparna Das
金额:
$8.99万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2012
资助国家:
美国
项目状态:
已结题
起止时间:
2012-09-15 至 2014-08-31
中文摘要
这项研究旨在克服实现1000核(千核)处理器所需要解决的极端挑战。如今,拥有数十个核心的处理器已经出现在商业产品中。千核处理器可以把我们带入服务器芯片和超级计算机芯片的时代。片上网络是处理器中两个节点进行通信的媒介,因此构成了千核处理器的骨干。不幸的是,目前的片上网络解决方案是不够的,因为它们在功率和性能方面都不能扩展到几十个内核以上。为了在实际的功耗预算下实现1000+核的宏伟设计目标,互连技术需要至少提高15倍的功耗效率,同时提供至少与目前相同的每核吞吐量水平。这个项目研究了三个相互关联的解决方案,以一种渐进的方式来应对上述挑战:(1)开发一种低功耗和能量比例的互连架构,采用更多的窄网络;(2)使用高基数Swizzle-Switches作为多个网络互连的构建块;(3)重新设计具有多个网络和Swizzle-Switches的网络架构,使用3D集成与through silicon - vias实现超过1000核的可扩展性。这个项目将展示千核处理器的可行性。如果这样的处理器能够建成,它们可能会对未来的百亿亿级系统产生巨大影响,比如云计算服务器和高性能计算系统,这些系统有许多应用,包括药物发现、国防、信息分析和社交网络。
英文摘要
This research aims to overcome the extreme challenges that need to be solved to realize a 1000-core (kilocore) processor. Processors with tens of cores are already in commercial products today. A kilocore processor could take us into the era of Server-on-Chip and Supercomputer-on-Chip. On-chip network is the medium through which two nodes in a processor can communicate, and therefore constitutes the backbone of a kilocore processor. Unfortunately, current on-chip network solutions are inadequate as they do not scale in terms of both power and performance beyond a few tens of cores. To reach the ambitious design goal of 1000+ cores with realistic power budgets, the interconnect technology needs to be at least 15 times more power efficient while providing at least the same level of throughput-per-core as today. This project investigates three interrelated solutions to meet the above challenge in an evolutionary manner: (1) Developing a low-power and energy-proportional interconnect architecture that employs a larger number of narrower networks, (2) Using high-radix Swizzle-Switches as the building blocks for interconnecting the multiple networks, and (3) Re-designing network architecture with multiple networks and Swizzle-Switches using 3D integration with Through-Silicon-Vias to achieve scalability beyond 1000 cores. This project will demonstrate the feasibility of kilocore processors. If such processors can be built, they could have a tremendous impact on future exascale systems such as cloud computing servers and HPC systems that have many applications including drug discovery, defense, information analysis, and social networking.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
RAPID: Pathogen Detection with Real-Time Genetic Sequencing
-
批准号:2030454
-
项目类别:Standard Grant
-
资助金额:$20.0万
-
财政年份:2020
-
负责人:Reetuparna Das
-
依托单位:
SHF: Small: Acceleration Using Smart Memory-on-Chip
-
批准号:1908601
-
项目类别:Standard Grant
-
资助金额:$45.0万
-
财政年份:2019
-
负责人:Reetuparna Das
-
依托单位:
SHF: Compute Caches: Opportunistic Parallelism in General Purpose Processors at Extreme Scale
-
批准号:1763918
-
项目类别:Standard Grant
-
资助金额:$30.0万
-
财政年份:2018
-
负责人:Reetuparna Das
-
依托单位:
CAREER: In-Situ Compute Memories for Accelerating Data Parallel Applications
-
批准号:1652294
-
项目类别:Continuing Grant
-
资助金额:$57.36万
-
财政年份:2017
-
负责人:Reetuparna Das
-
依托单位:
海外基金