SBIR Phase II: In-Memory Artificial Neural Network

SBIR 第二阶段：内存人工神经网络

• 批准号: 1831151
• 负责人: Wolfgang Hokenmaier
• 金额: $ 75万
• 依托单位: Green Mountain Semiconductor, Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-09-01 至 2021-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1831151&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Memory; Artificial

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is provided by a novel data processing architecture, utilizing high-parallel in-memory computing for certain recurring and data intensive functions. Traditional computer architecture funnels all data through the central processing unit (CPU). Multiple CPU cores and very high clock frequencies are used to address the issue of ever increasing demands on data processing capability. However, the transportation capacity of data between memory and CPU cores has become a limiting factor creating a 'memory bottleneck'. This limitation is most noticeable in the recent and rapid development of artificial intelligence applications which deploy so called neuromorphic computing techniques, which in turn require a very high parallelism in computation and proportional demands on memory bandwidth. This project performs key repetitive operations within the memory itself, leveraging the inherent parallelism of the memory architecture, thereby avoiding a large percentage of the data transport otherwise required. The resulting elimination of the memory bottleneck provides a path forward for high complexity neuromorphic computing applications such as autonomous navigation used for self-driving cars. Reduced demands on data transport and CPU also significantly reduce power consumption, enabling a wide variety of mobile artificial intelligence applications.The proposed project investigates the system level integration challenges of a memory-centric neuromorphic computing approach, and aims to demonstrate a seamless integration with existing software platforms currently using traditional neuromorphic computing processors. It is important for a novel hardware platform to be compatible with existing software in order to lower barriers to market entry. This Phase II project also develops the actual semiconductor product which has been investigated in Phase I as a feasibility demonstrator. The Phase II product is based on a non-volatile high density memory architecture, and as such is expected to provide the full capability in terms of both power and operations per second. Once the hardware is available in the second half of the project, these key parameters will be thoroughly characterized and benchmarked against the current state of the art technology. A projection will be made outlining the future scaling potential using ultra high density volatile and non-volatile memory geared towards high complexity neuromorphic computing beyond what is currently possible using existing approaches.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这个小企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力是由一个新的数据处理架构提供的，该架构利用高并行内存计算来实现某些重复和数据密集型功能。传统的计算机体系结构通过中央处理器（CPU）传输所有数据。使用多个CPU内核和非常高的时钟频率来解决对数据处理能力不断增长的需求。然而，数据在内存和CPU内核之间的传输能力已经成为造成“内存瓶颈”的限制因素。这种限制在最近快速发展的人工智能应用程序中最为明显，这些应用程序部署了所谓的神经形态计算技术，这反过来又要求计算的高度并行性和对内存带宽的比例要求。这个项目在内存本身内执行关键的重复操作，利用内存架构固有的并行性，从而避免了大量的数据传输。由此消除的内存瓶颈为高复杂性神经形态计算应用（如用于自动驾驶汽车的自主导航）提供了一条前进的道路。降低对数据传输和CPU的需求也显著降低了功耗，使各种移动人工智能应用成为可能。该项目研究了以内存为中心的神经形态计算方法的系统级集成挑战，旨在演示与现有软件平台的无缝集成，目前使用传统的神经形态计算处理器。为了降低进入市场的门槛，新的硬件平台必须与现有软件兼容。该二期项目还开发了实际的半导体产品，该产品已在一期中作为可行性演示品进行了研究。第二阶段的产品基于非易失性高密度存储器架构，因此有望在功率和每秒操作次数方面提供完整的功能。一旦硬件在项目的后半段可用，这些关键参数将根据当前的技术状态进行彻底的表征和基准测试。我们将概述未来使用超高密度易失性和非易失性存储器的扩展潜力，这些存储器将超越目前使用现有方法所能实现的高度复杂的神经形态计算。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

An analysis of an inexpensive memory test solution

廉价内存测试解决方案的分析

• DOI: 10.1109/natw.2018.8388866
• 发表时间: 2018
• 期刊: 2018 IEEE 27th North Atlantic Test Workshop (NATW
• 作者: Pennucci, Ryan;Jurasek, Ryan;Hokenmaier, Wolfgang;Patrick, Lester;Bucci, Jacob;Labrecque, Donald;Kinney, David
• 通讯作者: Kinney, David

Verification and Testing Considerations of an In-Memory AI Chip

内存 AI 芯片的验证和测试注意事项

• DOI: 10.1109/natw49237.2020.9153079
• 发表时间: 2020
• 期刊: 2020 IEEE 29th North Atlantic Test Workshop (NATW
• 作者: Golmohamadi, Marcia;Jurasek, Ryan;Hokenmaier, Wolfgang;Labrecque, Don;Zhi, Ruoyu;Dale, Bret;Islam, Nibir;Kinney, Dave;Johnson, Angela
• 通讯作者: Johnson, Angela

Opportunities and Limitations of in-Memory Multiply-and-Accumulate Arrays

内存乘法累加数组的机会和局限性

• DOI: 10.1109/mdts52103.2021.9476104
• 发表时间: 2021
• 期刊: 2021 IEEE Microelectronics Design & Test Symposium (MDTS
• 作者: Zhi, Ruoyu;Jurasek, Ryan;Hokenmaier, Wolfgang;Labrecque, Don;Bucci, Jacob;Dale, Bret;Islam, Nibir;Kinney, Dave;Johnson, Angela
• 通讯作者: Johnson, Angela