Jitter-Tolerant Multi-Carrier ADC-Based Serial Link Architectures

基于抗抖动多载波 ADC 的串行链路架构

• 批准号: 1930828
• 负责人: Sebastian Hoyos
• 金额: $ 39万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-09-01 至 2023-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1930828&HistoricalAwards=false
• 关键词: Jitter; Tolerant; Multi; Carrier; ADC

The proposed multi-channel schemes in conjunction with the novel reconfigurable analog-to-digital-converter (ADC) architecture will lead to revolutionary relaxation of the clock variations and uncertainty caused by induced noise from the system electronics. The research will produce a broad and long lasting impact in the design and implementation of communication systems. The result will be a key to enable future transformative communications and signal processing applications such as portable fast imaging, wireless networks of handheld and wearable computing receivers, software-defined radios, cognitive radio spectrum sensing, millimeter-wave radios for safety (e.g., automotive collision avoidance radar), homeland security, and national defense. This project will include an interdisciplinary educational program involving training of graduate students and outreach activities to foster the representation of students from underrepresented groups. These activities will also include local, national, and international short courses and workshop presentations on topics related to the multidisciplinary research activities. The results of the proposed research activities will be disseminated broadly in national and international conferences and publications, and locally via the Trans-Texas Videoconference Network, which is a system that serves numerous colleges including eleven campuses of Texas A&M University and K-12 school districts.The ever-increasing data rates of modern serial link transceivers call for innovative architectures capable of overcoming several critical impairments, such as limited channel bandwidth and clock jitter, while complying with tight power budgets. Classical mixed-signal and ADC-based architectures took advantage of semiconductor technology scaling, but could only provide incremental improvements not able to satisfy the demand of much higher data rates in future wireline communication systems. This proposal will investigate a receiver architecture based on a frequency-domain ADC topology, a special class of analog-to-digital converters that makes an analog-domain transformation to frequency-domain before realizing quantization. Such transformation provides a simulated six-time relaxation in clock jitter requirements and a scalable solution that channelizes the receiver front end in analog domain. This allows easy reconfiguration to accommodate different data rates and modulation standards. Such a receiver architecture requires a well-matched transmitter topology to alleviate the impact of transmitter jitter across channels and modulation formats. The proposed ADC-based high-speed serial link design techniques aim to significantly improve jitter robustness and reduce ADC resolution and digital equalization complexity by utilizing a power-optimum frequency-channelized ADC-based receiver for symbol detection. The project will investigate three topics: (1) A novel energy-efficient multi-carrier transmitter architecture and a new serial link receiver architecture capable of providing baseband jitter robustness and coherent multi-tone modulation applications, based on the novel reconfigurable frequency-domain ADC. (2) Novel techniques to improve the speed and efficiency of a pipeline successive-approximation-register (SAR) sub-ADC, including a design that utilizes open-loop correlated level-shifting residue amplification to enable per-channel operation with a scalable resolution. (3) Efficient digital reconstruction, equalization, and inter-channel interference filters for symbol detection.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

所提出的多通道方案结合新颖的可重构模数转换器（ADC）架构，将导致革命性的放松的时钟变化和不确定性引起的系统电子设备的感应噪声。该研究将对通信系统的设计和实施产生广泛而持久的影响。其结果将是实现未来变革性通信和信号处理应用的关键，例如便携式快速成像、手持和可穿戴计算接收器的无线网络、软件定义无线电、认知无线电频谱感测、用于安全的毫米波无线电（例如，汽车防撞雷达）、国土安全和国防。该项目将包括一个跨学科教育方案，涉及研究生培训和外联活动，以促进代表性不足群体的学生的代表性。这些活动还将包括地方，国家和国际短期课程和研讨会介绍有关的多学科研究活动的主题。 拟议的研究活动的结果将在国家和国际会议和出版物中广泛传播，并通过跨德克萨斯州视频会议网络在当地传播，该网络是一个服务于包括德克萨斯州A& M大学和K-12学区的11个校区在内的众多学院的系统。现代串行链路收发器不断增加的数据速率要求能够克服几个关键缺陷的创新架构，例如有限的信道带宽和时钟抖动，同时遵守严格的功率预算。经典的混合信号和基于ADC的架构利用了半导体技术的缩放，但只能提供增量改进，无法满足未来有线通信系统中更高数据速率的需求。本提案将研究基于频域ADC拓扑结构的接收器架构，频域ADC拓扑结构是一类特殊的模数转换器，其在实现量化之前进行模拟域到频域的变换。这种转换提供了模拟的时钟抖动要求的六倍松弛，以及在模拟域中对接收器前端进行信道化的可扩展解决方案。这允许容易地重新配置以适应不同的数据速率和调制标准。这样的接收器架构需要良好匹配的发射器拓扑以减轻跨信道和调制格式的发射器抖动的影响。所提出的基于ADC的高速串行链路设计技术旨在通过利用功率最优频率信道化的基于ADC的接收器进行符号检测来显著提高抖动鲁棒性并降低ADC分辨率和数字均衡复杂度。该项目将研究三个主题：（1）基于新型可重构频域ADC的新型节能多载波发射机架构和新型串行链路接收机架构，能够提供基带抖动鲁棒性和相干多音调制应用。(2)本发明公开了用于提高流水线逐次逼近寄存器（SAR）子ADC的速度和效率的新颖技术，包括利用开环相关电平移位残差放大来实现具有可缩放分辨率的每通道操作的设计。(3)用于符号检测的高效数字重建、均衡和通道间干扰滤波器。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET

采用 22nm FinFET 封装、具有速度增强型自举开关的 38GS/s 7b 时间交错流水线 SAR ADC

• DOI: 10.1109/cicc53496.2022.9772785
• 发表时间: 2022
• 期刊: 2022 IEEE Custom Integrated Circuits Conference (CICC
• 作者: Zhu, Yuanming;Liu, Tong;Kaile, Srujan Kumar;Kiran, Shiva;Yi, II-Min;Liu, Ruida;Gomez Diaz, Julian Camilo;Hoyos, Sebastian;Palermo, Samuel
• 通讯作者: Palermo, Samuel

A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET

采用 22nm FinFET 的基于 ADC 的抗抖动 40Gb/s 多载波接收器前端

• DOI: 10.1109/cicc53496.2022.9772868
• 发表时间: 2022
• 期刊: 2022 IEEE Custom Integrated Circuits Conference (CICC
• 作者: Zhu, Yuanming;Gomez Diaz, Julian Camilo;Kumar Kaile, Srujan;Yi, II-Min;Liu, Tong;Hoyos, Sebastian;Palermo, Samuel
• 通讯作者: Palermo, Samuel