Jitter-Tolerant Multi-Carrier ADC-Based Serial Link Architectures

所提出的多通道方案与新颖的可重构模数转换器（ADC）架构相结合，将导致由系统电子器件引起的诱导噪声引起的时钟变化和不确定性的革命性放松。这项研究将对通信系统的设计和实施产生广泛而持久的影响。该成果将成为未来变革性通信和信号处理应用的关键，如便携式快速成像、手持和可穿戴计算接收器的无线网络、软件定义无线电、认知无线电频谱传感、用于安全的毫米波无线电（如汽车防撞雷达）、国土安全和国防。该项目将包括一个跨学科的教育计划，包括研究生培训和外展活动，以促进来自代表性不足群体的学生的代表性。这些活动还将包括与多学科研究活动有关的地方、国家和国际短期课程和讲习班报告。拟议的研究活动的结果将在国内和国际会议和出版物中广泛传播，并通过跨德克萨斯视频会议网络在当地传播，该网络是一个为许多学院服务的系统，包括德克萨斯州农工大学的11个校区和K-12学区。现代串行链路收发器的数据速率不断增加，需要能够克服几个关键缺陷的创新架构，例如有限的信道带宽和时钟抖动，同时符合紧张的功率预算。传统的混合信号和基于adc的架构利用了半导体技术的可扩展性，但只能提供增量改进，无法满足未来有线通信系统中更高数据速率的需求。本提案将研究基于频域ADC拓扑的接收器架构，这是一类特殊的模数转换器，在实现量化之前将模拟域转换为频域。这种转换提供了时钟抖动要求的模拟六倍松弛和可扩展的解决方案，在模拟域信道化接收器前端。这允许容易的重新配置，以适应不同的数据速率和调制标准。这样的接收器架构需要一个匹配良好的发射器拓扑结构，以减轻发射器跨信道和调制格式抖动的影响。所提出的基于ADC的高速串行链路设计技术旨在通过利用功率最优频率信道化ADC接收器进行符号检测，显著提高抖动鲁棒性，降低ADC分辨率和数字均衡复杂性。该项目将研究三个主题：(1)基于新型可重构频域ADC的新型节能多载波发射机架构和新型串行链路接收器架构，能够提供基带抖动鲁棒性和相干多音调制应用。(2)提高流水线逐次逼近寄存器（SAR）子adc的速度和效率的新技术，包括利用开环相关电平移位残差放大的设计，以实现可扩展分辨率的每通道操作。(3)用于符号检测的高效数字重构、均衡和信道间干扰滤波器。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The proposed multi-channel schemes in conjunction with the novel reconfigurable analog-to-digital-converter (ADC) architecture will lead to revolutionary relaxation of the clock variations and uncertainty caused by induced noise from the system electronics. The research will produce a broad and long lasting impact in the design and implementation of communication systems. The result will be a key to enable future transformative communications and signal processing applications such as portable fast imaging, wireless networks of handheld and wearable computing receivers, software-defined radios, cognitive radio spectrum sensing, millimeter-wave radios for safety (e.g., automotive collision avoidance radar), homeland security, and national defense. This project will include an interdisciplinary educational program involving training of graduate students and outreach activities to foster the representation of students from underrepresented groups. These activities will also include local, national, and international short courses and workshop presentations on topics related to the multidisciplinary research activities. The results of the proposed research activities will be disseminated broadly in national and international conferences and publications, and locally via the Trans-Texas Videoconference Network, which is a system that serves numerous colleges including eleven campuses of Texas A&M University and K-12 school districts.The ever-increasing data rates of modern serial link transceivers call for innovative architectures capable of overcoming several critical impairments, such as limited channel bandwidth and clock jitter, while complying with tight power budgets. Classical mixed-signal and ADC-based architectures took advantage of semiconductor technology scaling, but could only provide incremental improvements not able to satisfy the demand of much higher data rates in future wireline communication systems. This proposal will investigate a receiver architecture based on a frequency-domain ADC topology, a special class of analog-to-digital converters that makes an analog-domain transformation to frequency-domain before realizing quantization. Such transformation provides a simulated six-time relaxation in clock jitter requirements and a scalable solution that channelizes the receiver front end in analog domain. This allows easy reconfiguration to accommodate different data rates and modulation standards. Such a receiver architecture requires a well-matched transmitter topology to alleviate the impact of transmitter jitter across channels and modulation formats. The proposed ADC-based high-speed serial link design techniques aim to significantly improve jitter robustness and reduce ADC resolution and digital equalization complexity by utilizing a power-optimum frequency-channelized ADC-based receiver for symbol detection. The project will investigate three topics: (1) A novel energy-efficient multi-carrier transmitter architecture and a new serial link receiver architecture capable of providing baseband jitter robustness and coherent multi-tone modulation applications, based on the novel reconfigurable frequency-domain ADC. (2) Novel techniques to improve the speed and efficiency of a pipeline successive-approximation-register (SAR) sub-ADC, including a design that utilizes open-loop correlated level-shifting residue amplification to enable per-channel operation with a scalable resolution. (3) Efficient digital reconstruction, equalization, and inter-channel interference filters for symbol detection.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.