Jitter-Tolerant Multi-Carrier ADC-Based Serial Link Architectures

所提出的多通道方案与新颖的可重构模数转换器(ADC)结构相结合，将导致由系统电子感应噪声引起的时钟变化和不确定性的革命性放松。这项研究将对通信系统的设计和实现产生广泛和持久的影响。这一成果将成为实现未来变革性通信和信号处理应用的关键，例如便携式快速成像、手持和可穿戴计算接收器的无线网络、软件定义无线电、认知无线电频谱传感、用于安全的毫米波无线电(例如汽车防撞雷达)、国土安全和国防。该项目将包括一个跨学科教育方案，涉及对研究生的培训和促进代表性不足群体的学生代表性的外联活动。这些活动还将包括地方、国家和国际短期课程，以及关于与多学科研究活动有关的主题的研讨会报告。拟议的研究活动的结果将在国内和国际会议和出版物中广泛传播，并通过跨德克萨斯视频会议网络在当地传播，该网络是一个服务于众多大学的系统，包括德克萨斯农工大学和K-12学区的11个校区。现代串行链路收发器不断增长的数据速率要求创新的体系结构，能够在遵守紧张的电力预算的同时克服几个关键缺陷，如有限的信道带宽和时钟抖动。传统的基于混合信号和ADC的架构利用了半导体技术的规模优势，但只能提供增量改进，无法满足未来有线通信系统对更高数据速率的需求。该方案将研究一种基于频域ADC拓扑的接收器架构，这是一类特殊的模数转换器，在实现量化之前进行模拟域到频域的转换。这种转换提供了时钟抖动要求的模拟六倍松弛，以及在模拟域中将接收器前端通道化的可扩展解决方案。这允许轻松重新配置以适应不同的数据速率和调制标准。这样的接收器架构需要匹配良好的发送器拓扑，以减轻发送器跨通道和调制格式抖动的影响。所提出的基于ADC的高速串行链路设计技术旨在通过使用基于功率最优频率信道化ADC的接收器进行符号检测来显著提高抖动稳健性、降低ADC分辨率和数字均衡复杂度。该项目将研究三个主题：(1)基于新型可重构频域ADC的新型节能多载波发射机体系结构和能够提供基带抖动鲁棒性和相干多音调制应用的新的串行链路接收器体系结构。(2)提高流水线逐次逼近寄存器(SAR)子ADC的速度和效率的新技术，包括一种利用开环相关电平移位剩余放大来实现具有可扩展分辨率的每通道操作的设计。(3)用于符号检测的高效数字重建、均衡和通道间干扰过滤器。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The proposed multi-channel schemes in conjunction with the novel reconfigurable analog-to-digital-converter (ADC) architecture will lead to revolutionary relaxation of the clock variations and uncertainty caused by induced noise from the system electronics. The research will produce a broad and long lasting impact in the design and implementation of communication systems. The result will be a key to enable future transformative communications and signal processing applications such as portable fast imaging, wireless networks of handheld and wearable computing receivers, software-defined radios, cognitive radio spectrum sensing, millimeter-wave radios for safety (e.g., automotive collision avoidance radar), homeland security, and national defense. This project will include an interdisciplinary educational program involving training of graduate students and outreach activities to foster the representation of students from underrepresented groups. These activities will also include local, national, and international short courses and workshop presentations on topics related to the multidisciplinary research activities. The results of the proposed research activities will be disseminated broadly in national and international conferences and publications, and locally via the Trans-Texas Videoconference Network, which is a system that serves numerous colleges including eleven campuses of Texas A&M University and K-12 school districts.The ever-increasing data rates of modern serial link transceivers call for innovative architectures capable of overcoming several critical impairments, such as limited channel bandwidth and clock jitter, while complying with tight power budgets. Classical mixed-signal and ADC-based architectures took advantage of semiconductor technology scaling, but could only provide incremental improvements not able to satisfy the demand of much higher data rates in future wireline communication systems. This proposal will investigate a receiver architecture based on a frequency-domain ADC topology, a special class of analog-to-digital converters that makes an analog-domain transformation to frequency-domain before realizing quantization. Such transformation provides a simulated six-time relaxation in clock jitter requirements and a scalable solution that channelizes the receiver front end in analog domain. This allows easy reconfiguration to accommodate different data rates and modulation standards. Such a receiver architecture requires a well-matched transmitter topology to alleviate the impact of transmitter jitter across channels and modulation formats. The proposed ADC-based high-speed serial link design techniques aim to significantly improve jitter robustness and reduce ADC resolution and digital equalization complexity by utilizing a power-optimum frequency-channelized ADC-based receiver for symbol detection. The project will investigate three topics: (1) A novel energy-efficient multi-carrier transmitter architecture and a new serial link receiver architecture capable of providing baseband jitter robustness and coherent multi-tone modulation applications, based on the novel reconfigurable frequency-domain ADC. (2) Novel techniques to improve the speed and efficiency of a pipeline successive-approximation-register (SAR) sub-ADC, including a design that utilizes open-loop correlated level-shifting residue amplification to enable per-channel operation with a scalable resolution. (3) Efficient digital reconstruction, equalization, and inter-channel interference filters for symbol detection.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.