Collaborative Research: SHF: Small: Optimization of Memory Architectures: A Foundation Approach

本项目提出了一种模型驱动的现代计算机体系结构内存系统性能优化的基本方法，并开发了一套内存体系结构优化方法和工具，这些方法和工具在理论上被证明是现代内存体系结构设计的经验可行的。该项目的成果将显著改善现代计算机系统中设计和评估内存体系结构的性能建模和优化技术，这些系统具有深度和多样化的内存系统层次，异构存储设备以及复杂的数据密集型应用，包括大数据，云和数据中心以及高性能计算应用。该项目的研究结果将改进pi教授的各种课程的内容。该项目计划利用印度理工学院，特别是为少数民族服务的国际财经大学的制度努力，积极招收少数民族学生。该项目将把教育和推广活动与现有的研究和教育中心结合起来。CPU和内存之间的速度差距越来越大，导致内存访问成为现代计算机体系结构中一个严重的性能瓶颈。在过去的25年里，解决这一“内存墙”问题的尝试支撑了计算机体系结构设计的技术创新。该研究的目的是显著扩展先前的内存模型，并创建一个实用的内存架构性能建模和优化框架，该框架可以捕获数据局域性、数据并发性、访问延迟和实际应用程序和实际系统上的多层内存架构的综合影响。仿真驱动的方法将通过详细的实际系统测量和性能分析来开发，以检查潜在的好处并确定各种内存体系结构设计的性能问题。更具体地说，该项目将沿着三个研究方向发展：(1)发展理论和体系结构基础，以解决与分层异构存储体系结构相关的基本问题，并研究应用各种存储体系结构的建模和优化框架的实际方面；(2)针对特定内存架构进行模型驱动的内存架构设计和优化，包括分解内存系统、GPU和包含非易失性存储器的混合存储设备的深度内存层次；(3)开发嵌入性能建模和优化框架的内存架构模拟器，并进行仿真研究和实际系统测量，以评估内存性能，并比较设计方案和权衡。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

This project proposes a foundational approach to model-driven performance optimization of memory systems for modern computer architectures, with the development of a set of memory-architecture optimization methods and tools that are theoretically proven and empirically feasible for modern memory architecture design. The outcome of this project will significantly improve the performance modeling and optimization techniques for designing and evaluating memory architectures in modern computer systems, featuring deep and diverse memory-system hierarchies, heterogeneous memory devices, and complex data-intensive applications, including big-data, cloud and data centers and high-performance computing applications. The findings of this project will improve the content of various courses that the PIs teach. This project plans to proactively recruit minority students by taking advantage of the institutional efforts at IIT and especially at FIU, which is a minority-serving institution. This project will align education and outreach activities with an existing research and education center.The growing disparity between CPU and memory speed causes memory accesses to become a severe performance bottleneck in modern computer architectures. Attempts to solving this “memory wall” problem underpin technological innovations in computer-architecture design over the last two and half decades. The objective of the research is to significantly extend prior memory models and create a practical memory-architecture performance-modeling and optimization framework that can capture the combined effects of data locality, data concurrency, access latency, and multi-tier memory architecture for real applications and on real systems. A simulation-driven approach will be developed with elaborate real-system measurements and performance analyses to examine the potential benefits and identify the performance issues of various memory-architecture designs. More specifically, this project will develop along three research directions: (1) developing theoretical and architectural foundations to address both fundamental questions related to the tiered heterogeneous memory architectures and investigate practical aspects of applying the modeling and optimization framework for various memory architectures; (2) performing model-driven memory-architecture design and optimization for specific memory architectures, including disaggregated memory system, GPU, and deep-memory hierarchy with hybrid memory devices including non-volatile memory; and (3) developing the memory architecture simulator embedded with the performance modeling and optimization framework, and conducting simulation studies and real system measurements to evaluate memory performance, and compare design alternatives and trade-offs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.