STTR Phase I: A Software Platform for Assessment of Untrusted Electronics

这个小型企业技术转让（STTR）第一阶段项目的更广泛的影响/商业潜力是解决集成电路（IC）设计和电子设计自动化（EDA）软件市场目前存在的安全挑战。 它将创建一个使用不受信任的第三方知识产权块的集成电路“安全设计”平台。它将为半导体设计人员提供一种工具，可以自动分析安全漏洞并在制造之前解决这些漏洞。这种能力将导致制造的芯片和它们集成到其中的系统的安全改进，同时还通过漏洞分析和缓解的自动化来减少安全系统设计的成本和时间。这项小型企业技术转移（STTR）第一阶段项目将开发一个网表评估工具集，用于分析现代片上系统（SoC）设计中使用的第三方集成电路（IC）设计模块的门级网表。 该工具集将门级网表转换为可读格式，以支持电子设计自动化（EDA）软件市场中现有的安全分析工具。 在门级安全分析期间，该工具集将能够检测设计中的盗版、逆向工程以及恶意逻辑的漏洞。为了使EDA和半导体行业的客户能够进入工具集市场，SBIR/STTR第一阶段项目将主要关注可扩展性测试、接口设计、安全优势分析和性能改进。该工具集的可扩展性测试将在内部进行，并与EDA行业客户一起进行，以证明该工具集在分析和转换大规模SoC的门级网表方面的能力。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Technology Transfer (STTR) Phase I project is to address the security challenges that currently exist in integrated circuit (IC) design and the electronic design automation (EDA) software market. It will create a platform for ‘secure-by-design' of integrated circuits using untrusted third-party intellectual property blocks. It will provide a tool to semiconductor designers to automatically analyze security vulnerabilities and address them before fabrication. Such a capability will lead to security improvement of the fabricated chips and the systems they are integrated into, while also reducing the cost and time for secure system design through automation of vulnerability analysis and mitigation. The proposed toolset will address a critical technology gap in the semiconductor design and EDA marketplace.This Small Business Technology Transfer (STTR) Phase I project will develop a netlist assessment toolset which analyzes gate-level netlist of third-party integrated circuit (IC) design blocks used in modern system-on-chip (SoC) designs. The toolset converts the gate-level netlist to readable formats to support the existing security analysis tools in the electronic design automation (EDA) software market. During gate-level security analysis, this toolset will enable the detection of vulnerability for piracy, reverse engineering, as well as malicious logic in a design. To make the toolset market ready for our customers in the EDA and semiconductor industry, the SBIR/STTR Phase I project will mainly focus on scalability testing, interface design, analysis of security benefits, and performance improvement. Scalability testing of the toolset will be performed internally and with EDA industry customers to demonstrate the capability of the toolset in analyzing and converting the gate-level netlist of large scale SoCs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.