CRII: SHF: Enabling Metal Inter-Layer Via Device Utilization for On-chip Memory in Monolithic Three-Dimensional Integrated Circuits

CRII:SHF:通过器件利用金属层间通孔实现单片三维集成电路中的片上存储器

基本信息

  • 批准号:
    2105164
  • 负责人:
  • 金额:
    $ 17.49万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2021
  • 资助国家:
    美国
  • 起止时间:
    2021-07-15 至 2023-12-31
  • 项目状态:
    已结题

项目摘要

A monolithic three-dimensional integrated circuit (M3D IC) is a promising technology to meet future computational demands as transistor density increases due to the vertical dimension. This project addresses one of the primary design challenges associated with the M3D IC technology to realize energy-efficient and compact integrated chips. The project is facilitating further advances in M3D IC technology by providing novel device models and design strategies for integrated chips to the research community. The investigator is developing a participation plan to involve students from the underrepresented groups in the field of integrated circuits through this project. The techniques developed in this research are intended to be used to develop computer-engineering courses and also to be presented in technical seminars for industry collaborations.In M3D IC technology, the substrate layers are realized sequentially, and these layers are connected through metal inter-layer vias (MIVs). This project aims to develop small footprint and efficient M3D IC designs by opportunistically utilizing substrate area around MIV to form MIV-devices specifically MIV-capacitor and MIV-transistor. This brings in new challenges for designing and characterizing MIV-devices to optimize the form factor and efficiency. These challenges are addressed by this project through 1) developing SPICE models for proposed MIV-devices in M3D-IC technology, and 2) utilizing these MIV-devices for on-chip static random-access memory (SRAM) and dynamic random-access memory (DRAM) to enable compact and power-efficient M3D ICs. The techniques developed in this research are providing future opportunities for M3D IC technology at all design levels – device, circuit, and computer-aided design. The results of this project are intended to lay a foundation for a design framework for full-scale M3D IC designs to meet future computational requirements.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
单片三维集成电路(M3 D IC)是一种很有前途的技术,以满足未来的计算需求,晶体管密度增加,由于垂直尺寸。该项目解决了与M3 D IC技术相关的主要设计挑战之一,以实现节能和紧凑的集成芯片。该项目通过为研究界提供新型器件模型和集成芯片设计策略,促进了M3 D IC技术的进一步发展。研究人员正在制定一项参与计划,使集成电路领域代表性不足的群体的学生参与该项目。本研究开发的技术旨在用于开发计算机工程课程,也将在技术研讨会上提出的产业合作。在M3 D IC技术中,基板层是顺序实现的,这些层通过金属层间通孔(MIV)连接。该项目旨在通过机会性地利用MIV周围的衬底区域来形成MIV器件(特别是MIV电容器和MIV晶体管),开发小尺寸和高效的M3 D IC设计。这为设计和表征MIV设备带来了新的挑战,以优化形状因子和效率。该项目通过以下方式解决这些挑战:1)为M3 D-IC技术中的MIV器件开发SPICE模型; 2)将这些MIV器件用于片上静态随机存取存储器(SRAM)和动态随机存取存储器(DRAM),以实现紧凑且节能的M3 D IC。在这项研究中开发的技术提供了未来的机会,M3 D IC技术在所有的设计水平-设备,电路和计算机辅助设计。该项目的成果旨在为全尺寸M3 D IC设计奠定基础,以满足未来的计算需求。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。

项目成果

期刊论文数量(6)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology
Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC
  • DOI:
    10.1109/access.2024.3363913
  • 发表时间:
    2024
  • 期刊:
  • 影响因子:
    3.9
  • 作者:
    M. Vemuri;Umamaheswara Rao Tida
  • 通讯作者:
    M. Vemuri;Umamaheswara Rao Tida
Design, Analysis and Optimization of Magnetic-Core Solenoid Inductor for On-Chip Multi-Phase Buck Converter
  • DOI:
    10.1109/access.2023.3281359
  • 发表时间:
    2023
  • 期刊:
  • 影响因子:
    3.9
  • 作者:
    Maliha Elma;M. Vemuri;Umamaheswara Rao Tida
  • 通讯作者:
    Maliha Elma;M. Vemuri;Umamaheswara Rao Tida
FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration
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Umamaheswara Tida其他文献

Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking
谐振时钟中的动态频率缩放感知机会硅通孔电感器利用

Umamaheswara Tida的其他文献

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