Collaborative Research: SHF: Small: Programmable Hierarchical Caches: Design, Programming, and Prototyping

合作研究：SHF：小型：可编程分层缓存：设计、编程和原型设计

• 批准号: 2114285
• 负责人: Dorin Patru
• 金额: $ 22.81万
• 依托单位: Rochester Institute of Tech
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-09-01 至 2025-08-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2114285&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Small; Programmable

As computing technology becomes ever more powerful, memory is larger but more complex, with different materials, configurations, and interconnects having different trade-offs among capacity, speed, and cost. Because of this complexity, fully automatic solutions are increasingly sub-optimal and brittle. This project develops new designs of the memory hierarchy that are programmable and therefore can achieve better performance and provide stronger guarantees than conventional solutions used on current computer systems ranging from smartphones to supercomputers. The new programmability enables optimization in software and hardware in concert. Since computer cost and speed depend on memory hierarchy, programmable designs can overcome the current limit in scalability and power efficiency. Beyond its technical content, the project advances teaching in the science of computer memory and strives to increase the diversity among participants in this area of research and development.Specifically, the project develops a two-level programmable cache system called the lease cache and designs its programming techniques. It has three parts: automatic programming and optimization of the lease cache; hardware design and prototyping of a RISC-V processor with the two-level lease cache on an FPGA board; and lease-cache theory especially statistical properties and guarantees of the cache performance. Through theories and prototyping, the new designs can retain software portability, ensure matching performance to current automatic solutions by default, and provide precisely defined cache performance properties.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着计算技术变得越来越强大，内存越来越大，但也越来越复杂，不同的材料、配置和互连在容量、速度和成本方面有着不同的权衡。由于这种复杂性，全自动解决方案越来越不理想且脆弱。该项目开发了可编程的内存层次结构的新设计，因此可以实现更好的性能，并提供比当前计算机系统（从智能手机到超级计算机）使用的传统解决方案更强的保证。新的可编程性使软件和硬件协同优化成为可能。由于计算机的成本和速度取决于存储器层次结构，可编程设计可以克服当前在可扩展性和功率效率方面的限制。除了技术内容之外，该项目还促进了计算机内存科学的教学，并努力增加这一研究和开发领域参与者的多样性。具体而言，该项目开发了一个两级可编程缓存系统，称为租约缓存，并设计了其编程技术。它包括三个部分：自动编程和优化租赁缓存；FPGA板上具有二级租约缓存的RISC-V处理器的硬件设计和原型设计；租期-缓存理论，特别是统计特性和缓存性能的保证。通过理论和原型设计，新设计可以保留软件可移植性，确保默认情况下与当前自动解决方案的性能匹配，并提供精确定义的缓存性能属性。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Cache Programming for Scientific Loops Using Leases

使用租约对科学循环进行缓存编程

• 发表时间: 2023
• 期刊: ACM transactions on architecture and code optimization
• 影响因子: 1.6
• 作者: Reber, Benjamin;Gould, Matthew;Kneipp, Alexander H.;Liu, Fangzhou;Prechtl, Ian;Ding, Chen;Chen, Linlin;Patru, Dorin
• 通讯作者: Patru, Dorin

Cache-coherent CLAM (WIP)

缓存一致性 CLAM (WIP)

• DOI: 10.1145/3519941.3535073
• 发表时间: 2022
• 期刊: Cache-Coherent CLAM (WIP
• 作者: Ding, Chen;Reber, Benjamin;Patru, Dorin
• 通讯作者: Patru, Dorin