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SaTC: CORE: Small: Formal Verification Techniques For Microprocessor Security Vulnerabilities and Trojans

SaTC: CORE: Small: Formal Verification Techniques For Microprocessor Security Vulnerabilities and Trojans
SaTC:核心:小型:微处理器安全漏洞和特洛伊木马的形式验证技术
批准号:
2117190
负责人:
Sudarshan Srinivasan
金额:
$35.22万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2021
资助国家:
美国
项目状态:
已结题
起止时间:
2021-10-01 至 2024-09-30

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中文摘要
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英文摘要
Microprocessors are circuits used to execute software programs and are used in important applications such as financial systems,ˇmedical devices, cars,ˇpower plants etc. Recently a method called Spectre was found that could leak private data from modern microprocessors. Several variations of Spectre have also been discovered. Formal verification is a set of techniques that use mathematical proofs to check if a design behaves correctly. Many such formal verificationˇtechniques have been developed for microprocessors. The goal of this project is to extend these formal verification techniques to check if microprocessor designs are vulnerable to Spectre and its variations. The intellectual merits of the project are the development of formal properties to check invulnerability of microprocessor designs to Spectre, Meltdown, and related security flaws. The checking of the properties will also flag bugs or trojans that can induce these flaws. The project will also study and develop refinement-maps, microprocessor-specific abstractions, invariants, compositional reasoning, and functional instantiation techniques required to ensure efficient and scalable verification. The research activities of the project are in themselves beneficial to society. Microprocessors are used pervasively and security is becoming a big hassle in this expansion. In addition, the project will aim to improve participation of women and underrepresented minorities in Computer Engineering by offering two-week summer courses on "Digital Electronics and Computer Design" with lab experience for high school students. The novel idea proposed to improve recruitment and participation will be to exploit the wide coverage of Spectre and Meltdown in the news media and the associated interest generated among students in microprocessor design and Computer Engineering.The project is expected to generate the following types of data: (1) Processor models and verification properties; (2) Python scripts written to generate verification benchmarks; (3) Papers that will be published in conferences and journals; and (4) Teaching materials such as power point slides, instruction manuals, and assignments. The data will be available on the project web page (see link below) hosted by North Dakota State University as long as it is of use either for research or teaching purposes to academics or industry.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(3)
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会议论文
DOI: 10.1049/cdt2.12058
发表时间: 2023
期刊: IET Computers & Digital Techniques
影响因子: 1.2
作者: [Ponugoti, Kushal K., Srinivasan, Sudarshan K., Mathure, Nimish]
通讯作者: Mathure, Nimish
A Refinement-Based Approach to Spectre Invulnerability Verification
一种基于细化的幽灵抗毁性验证方法
DOI: 10.1109/access.2022.3195508
发表时间: 2022
期刊: IEEE Access
影响因子: 3.9
作者: [Mathure, Nimish, Srinivasan, Sudarshan K., Ponugoti, Kushal K.]
通讯作者: Ponugoti, Kushal K.
Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits
用于检测管道电路中始终在线的拒绝服务木马的形式验证方法
DOI: 10.1109/icecs53924.2021.9665617
发表时间: 2021
期刊: and Systems (ICECS
影响因子: --
作者: [Ponugoti, Kushal K., Srinivasan, Sudarshan K., Mathure, Nimish]
通讯作者: Mathure, Nimish
SHF:Small:GOALI:Formal Equivalence Checking for Quasi-Delay-Insensitive Circuits
  • 批准号:
    1717420
  • 项目类别:
    Standard Grant
  • 资助金额:
    $45.0万
  • 财政年份:
    2017
  • 负责人:
    Sudarshan Srinivasan
  • 依托单位:
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  • 财政年份:
    2011
  • 负责人:
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