SHF:Small:GOALI:Formal Equivalence Checking for Quasi-Delay-Insensitive Circuits
SHF:Small:GOALI:Formal Equivalence Checking for Quasi-Delay-Insensitive Circuits
批准号:
1717420
负责人:
Sudarshan Srinivasan
金额:
$45.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2017
资助国家:
美国
项目状态:
已结题
起止时间:
2017-08-15 至 2022-07-31
中文摘要
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英文摘要
Digital integrated circuits (ICs) are designed based on a periodic signal called the clock, which synchronizes the operation of the components of an Integrated Circuit (IC) referred to as synchronous circuits. However, the rigidity of clock-based synchronous design causes the resulting ICs to malfunction in extreme environments (e.g., very hot/cold, large temperature swings, high radiation). An alternate approach to IC design is the asynchronous paradigm, where correct operation is achieved through the use of locally distributed handshaking protocols instead of a global synchronizing clock. Quasi-Delay-Insensitive (QDI) asynchronous circuits have been shown to function in extreme environments and also consume lower power compared to synchronous circuits. However, designing QDI circuits correctly is more difficult, because their behavior is much more complex and unconstrained. The goal of this project is to develop verification methodologies for QDI circuits, which will have a broad impact, enabling reliable design and therefore more widespread usage of QDI circuits in extreme environment and low-power Internet of Things (IoT) applications, such as space exploration, power industry, automobile industry, wireless sensor networks, etc. The project will have close collaboration with industry via transfer technology, and plans to prepare students for a career in the technical fields covered by this project.The proposed technical approach aims to develop a systematic proof technique that can be used to establish the functional equivalence of a QDI circuit with its synchronous counterpart. It is based on formal verification, where mathematical proofs are used to establish correctness of the design, or find anomalies if the design is not correct. The proposed approach exploits the fact that synchronous circuits are much easier to design and verify. Therefore, to verify a QDI circuit, the previously verified synchronous counterpart will be used as the reference.
期刊论文(8)
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Formal Modeling and Verification of PCHB Asynchronous Circuits
PCHB异步电路的形式化建模和验证
DOI:
10.1109/tvlsi.2019.2937087
发表时间:
2019
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI
影响因子:
--
作者:
[Sakib, Ashiq A., Smith, Scott C., Srinivasan, Sudarshan K.]
通讯作者:
Srinivasan, Sudarshan K.
DOI:
10.1049/cdt2.12047
发表时间:
2022-09
期刊:
IET Comput. Digit. Tech.
影响因子:
--
作者:
[Kushal K. Ponugoti;S. Srinivasan;S. Smith;Nimish Mathure]
通讯作者:
Kushal K. Ponugoti;S. Srinivasan;S. Smith;Nimish Mathure
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits
利用双轨寄存器不变量进行 NCL 电路的等效性验证
DOI:
--
发表时间:
2020
期刊:
63rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2020
影响因子:
--
作者:
[Le, Son, Srinivasan, Sudarshan, Smith, Scott.]
通讯作者:
Smith, Scott.
Automated verification of input completeness for NCL circuits
自动验证 NCL 电路的输入完整性
DOI:
10.1049/el.2018.6068
发表时间:
2018
期刊:
Electronics Letters
影响因子:
1.1
作者:
[Le, S., Srinivasan, S.K., Smith, S.C.]
通讯作者:
Smith, S.C.
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits
异步睡眠约定逻辑电路的等效验证方法
DOI:
10.1109/iscas.2019.8702098
发表时间:
2019
期刊:
2019 IEEE International Symposium on Circuits and Systems (ISCAS
影响因子:
--
作者:
[Hossain, Mousam, Sakib, Ashiq A., Srinivasan, Sudarshan K., Smith, Scott C.]
通讯作者:
Smith, Scott C.
共 8 条
SaTC: CORE: Small: Formal Verification Techniques For Microprocessor Security Vulnerabilities and Trojans
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批准号:2117190
-
项目类别:Standard Grant
-
资助金额:$35.22万
-
财政年份:2021
-
负责人:Sudarshan Srinivasan
-
依托单位:
SHF: Small:Methodologies and Tools For Verification of Nano-Pipelined Circuits and Systems
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批准号:1117164
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资助金额:$17.72万
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财政年份:2011
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负责人:Sudarshan Srinivasan
-
依托单位:
国内基金
海外基金
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