SHF: Small:Methodologies and Tools For Verification of Nano-Pipelined Circuits and Systems

SHF：小型：纳米管道电路和系统验证的方法和工具

• 批准号: 1117164
• 负责人: Sudarshan Srinivasan
• 金额: $ 17.72万
• 依托单位: North Dakota State University Fargo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-08-01 至 2015-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1117164&HistoricalAwards=false
• 关键词: SHF; Small; Methodologies; Tools; Verification

The continuing and accelerated advancement of nanotechnology promises a future in which computing will be truly ubiquitous. The ability to develop minuscule Integrated Chips that implement exceedingly complex systems will impact all aspects of human development ranging from medicine to space exploration. A majority of these applications will be safety critical applications in which the cost of failure will result in loss of human life and exceedingly high economic costs. Scalable verification technology at the nanoscale for developing reliable and bug-free designs is therefore a requirement for the growth and impact of digital systems in the nano-era. One of the key optimizations used extensively in digital design is hardware pipelining, which is similar in operation to the pipelined automotive assembly line. Pipeline implementations at the nanoscale are very complex and prone to errors. This research seeks to develop solutions to enable efficient and scalable verification of pipelined circuits and systems at the nanoscale. The verification solutions are based on refinement, a notion of equivalence used to compare systems defined at very disparate levels of abstraction. The overall approach is to use high-level refinement-based transformations to reduce the nano-pipelined circuit/system to be verified, in incremental steps, to a functionally equivalent non-pipelined synchronous machine. The non-pipelined machine can then be easily compared with high-level specifications using existing verification techniques.

纳米技术的持续和加速发展预示着一个计算将真正无处不在的未来。 开发实现极其复杂系统的微型集成芯片的能力将影响人类发展的各个方面，从医学到太空探索。 这些应用中的大多数将是安全关键应用，其中故障的成本将导致人的生命损失和极高的经济成本。因此，在纳米尺度上开发可靠和无缺陷设计的可扩展验证技术是纳米时代数字系统增长和影响的一个要求。 在数字设计中广泛使用的关键优化之一是硬件流水线，其操作类似于流水线汽车装配线。纳米级的流水线实现非常复杂并且容易出错。本研究旨在开发解决方案，以实现纳米级流水线电路和系统的高效和可扩展验证。验证解决方案是基于细化的，这是一种等价的概念，用于比较在不同抽象级别上定义的系统。总体方法是使用基于高级细化的变换来以增量步骤将待验证的纳米流水线电路/系统减少到功能等效的非流水线同步机。非流水线机器，然后可以很容易地比较使用现有的验证技术与高层次的规范。