GOALI: ASCENT: Wafer-Scale Computational System (WaSCoS) with heterogeneous integration, power-heat transport, and optical interconnects

晶片规模的系统有可能将一个机架的电子产品浓缩到一个晶片中，同时碳足迹要低得多。这项提案旨在探索和展示使这一潜力成为现实所需的技术。所关注的主要技术将是细间距异质集成，其中大量非常小和不同(即，异质)的电子部件(所谓的小芯片或小芯片)非常紧密地相互连接在一起；芯片之间的连接数量大约是今天传统系统的10到100倍。这两个功能大大缩小了系统的占用空间。传统的印刷电路板被大硅片取代，粗糙的焊接连接将被密度高10到100倍的微观无焊连接取代。这种系统的紧凑性意味着需要在更小的空间中提供更多的电力，需要从更小的空间中提取更多的热量。该系统可能实现的巨大计算密度需要使用结合高密度电连接器的精密微对准光纤来将数据移入和移出系统的新方法。这项技术将在摩尔关于芯片的定律停止的地方起飞，并允许计算能力的可持续扩展。这些技术的发展也将为我们的学生提供一种有价值和实用的学习工具，这将是封装和半导体技术计划中的制造业复兴所需的，也将流入由加州大学洛杉矶分校教师组织的现有扩展计划中，以吸引高中生进入STEM领域。该项目旨在生产一种系统，其中芯片在硅中频上组装到10-μm以下的节距(相比之下，500-μm球栅阵列(BGA)节距在传统印刷电路板上)。与使用精密对准热压缩键合的印刷电路板上通常看到的数十μm相比，Si-IF上的布线间距将是亚μm。这允许封装不同种类的芯片(处理器、内存、通信芯片等)。具有非常高的带宽、低延迟和每位低能耗-远远超出了当今最先进的硅插入器封装方法的指标。理想情况下，这样的方法将允许近10 TB的统一可访问内存，其二分带宽比目前的系统大近75倍，总带宽增加约250倍，平均延迟减少约40倍。这样的结果可以支持前所未有的计算工作量。除了芯片组装，这一目标面临的挑战还包括：合成此类系统所需的架构和设计基础设施需求；功率传输和散热解决方案，能够提供此类系统所需的预计25-kW，并安全高效地提取类似的热量；以及波分多路复用方法，能够提供高达20-100TB/S的数据，同时使用名为“FlexTrate”的灵活扇出晶圆级封装方法，同时符合足够小的外形系数。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Wafer-scale systems have the potential to condense a rack's worth of electronics into a single wafer along with a much lower carbon footprint. This proposal seeks to explore and demonstrate technologies needed to make this potential a reality. The main technology of concern will be fine-pitch heterogeneous integration, wherein a great number of very small and diverse (i.e. heterogeneous) electronic parts (so-called chiplets or dielets) are interconnected very closely together; the number of connections between the chips is about 10 to 100 times more than today’s conventional systems. These two features allow for shrinking the footprint of the system considerably. Traditional printed circuit boards are replaced by large silicon wafers and coarse soldered connections will be replaced by microscopic solderless welded connections that are 10 to 100 times denser. The compact nature of such systems means that more power needs to be delivered in a smaller space and more heat needs to be extracted from a smaller space. The immense computing density possible with this system requires new methods of moving data in and out of the system using precision micro-aligned optical fibers combined with high density electrical connectors. This technology will take off where Moore’s law for chips leaves off and allow for sustainable scaling of computing capabilities. The development of these technologies will also provide a valuable and practical learning vehicle for our students that will be needed for the manufacturing resurgence that is planned for packaging and semiconductor technology and will also flow into existing outreach programs to attract high school students organized by UCLA faculty to STEM fields.The project aims to produce a system wherein dies are assembled on Si-IF to pitches of sub-10-μm (compared to 500-μm ball grid array (BGA) pitches on a traditional printed circuit board). The wiring pitch on the Si-IF will be sub-μm, compared to the tens of μm typically seen on a PCB using precision aligned thermal compression bonding. This permits the packaging of heterogeneous dielets (processors, memory, communication chips, etc.) with very high bandwidth, low latency, and low energy per bit - well beyond the metrics of even the most advanced silicon interposer packaging approaches today. Ideally, such an approach will allow near 10-TB of uniformly accessible memory with bisection bandwidths near 75x larger than today’s systems, an aggregate bandwidth increase of about 250x and a uniform latency reduction of about 40x. Such results could support unprecedented workloads in computing. Aside from die assembly, challenges to this goal include architecture and design infrastructure needs for synthesizing such a system; power delivery and thermal dissipation solutions able to both provide the projected  25-kW required by such a system and safely and efficiently extract a similar amount in heat; and wavelength division multiplexing approaches capable of delivering up to 20-100 Tb/s of data while conforming to a sufficiently small form factor using a flexible fan-out wafer-level packaging approach titled "FlexTrate."This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.