GOALI: ASCENT: Wafer-Scale Computational System (WaSCoS) with heterogeneous integration, power-heat transport, and optical interconnects
目标:ASCENT:具有异构集成、功率热传输和光学互连的晶圆级计算系统 (WaSCoS)
基本信息
- 批准号:2231097
- 负责人:
- 金额:$ 131.86万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2022
- 资助国家:美国
- 起止时间:2022-10-01 至 2026-09-30
- 项目状态:未结题
- 来源:
- 关键词:
项目摘要
Wafer-scale systems have the potential to condense a rack's worth of electronics into a single wafer along with a much lower carbon footprint. This proposal seeks to explore and demonstrate technologies needed to make this potential a reality. The main technology of concern will be fine-pitch heterogeneous integration, wherein a great number of very small and diverse (i.e. heterogeneous) electronic parts (so-called chiplets or dielets) are interconnected very closely together; the number of connections between the chips is about 10 to 100 times more than today’s conventional systems. These two features allow for shrinking the footprint of the system considerably. Traditional printed circuit boards are replaced by large silicon wafers and coarse soldered connections will be replaced by microscopic solderless welded connections that are 10 to 100 times denser. The compact nature of such systems means that more power needs to be delivered in a smaller space and more heat needs to be extracted from a smaller space. The immense computing density possible with this system requires new methods of moving data in and out of the system using precision micro-aligned optical fibers combined with high density electrical connectors. This technology will take off where Moore’s law for chips leaves off and allow for sustainable scaling of computing capabilities. The development of these technologies will also provide a valuable and practical learning vehicle for our students that will be needed for the manufacturing resurgence that is planned for packaging and semiconductor technology and will also flow into existing outreach programs to attract high school students organized by UCLA faculty to STEM fields.The project aims to produce a system wherein dies are assembled on Si-IF to pitches of sub-10-μm (compared to 500-μm ball grid array (BGA) pitches on a traditional printed circuit board). The wiring pitch on the Si-IF will be sub-μm, compared to the tens of μm typically seen on a PCB using precision aligned thermal compression bonding. This permits the packaging of heterogeneous dielets (processors, memory, communication chips, etc.) with very high bandwidth, low latency, and low energy per bit - well beyond the metrics of even the most advanced silicon interposer packaging approaches today. Ideally, such an approach will allow near 10-TB of uniformly accessible memory with bisection bandwidths near 75x larger than today’s systems, an aggregate bandwidth increase of about 250x and a uniform latency reduction of about 40x. Such results could support unprecedented workloads in computing. Aside from die assembly, challenges to this goal include architecture and design infrastructure needs for synthesizing such a system; power delivery and thermal dissipation solutions able to both provide the projected 25-kW required by such a system and safely and efficiently extract a similar amount in heat; and wavelength division multiplexing approaches capable of delivering up to 20-100 Tb/s of data while conforming to a sufficiently small form factor using a flexible fan-out wafer-level packaging approach titled "FlexTrate."This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
晶圆级系统有可能将一个机架的电子产品浓缩到一个沿着的晶圆上,同时碳足迹要低得多。该提案旨在探索和展示实现这一潜力所需的技术。关注的主要技术将是细间距异构集成,其中大量非常小且不同的(即异构的)电子部件(所谓的小芯片或双芯片)非常紧密地互连在一起;芯片之间的连接数量比今天的传统系统多约10至100倍。这两个特征允许显著缩小系统的占用空间。传统的印刷电路板将被大型硅晶片所取代,粗糙的焊接连接将被密度为10到100倍的微观无焊焊接连接所取代。这种系统的紧凑性意味着需要在更小的空间中输送更多的功率,并且需要从更小的空间中提取更多的热量。该系统可能具有的巨大计算密度需要使用与高密度电连接器相结合的精密微对准光纤将数据移入和移出系统的新方法。这项技术将在芯片的摩尔定律停止的地方起飞,并允许计算能力的可持续扩展。这些技术的发展也将为我们的学生提供一个有价值的和实用的学习工具,这将是制造业复兴所需要的,计划用于包装和半导体技术,也将流入现有的推广计划,以吸引高中生组织的UCLA教师到STEM领域。该项目旨在生产一个系统,其中模具组装在Si-IF上,以低于10 μm的间距(与传统印刷电路板上的500 μm球栅阵列(BGA)间距相比)。Si-IF上的布线间距将低于μm,而使用精密对准热压键合的PCB上通常为数十μm。这允许封装异构设备(处理器、存储器、通信芯片等)。具有非常高的带宽、低延迟和低的每比特能量-远远超出了甚至当今最先进的硅中介层封装方法的度量。理想情况下,这种方法将允许接近10 TB的均匀可访问存储器,其二分带宽比今天的系统大近75倍,总带宽增加约250倍,均匀延迟减少约40倍。这样的结果可以支持前所未有的计算工作量。除了芯片组装之外,这一目标面临的挑战还包括综合这种系统的架构和设计基础设施需求;能够提供这种系统所需的预计25 kW功率并安全有效地提取类似热量的功率输送和散热解决方案;以及波分复用方法,其能够传送高达20-100 Tb/s的数据,同时符合足够小的形状因数,其使用名为“FlexTrate。“这个奖项反映了NSF的法定使命,并已被认为是值得通过使用基金会的知识价值和更广泛的影响审查标准进行评估的支持。
项目成果
期刊论文数量(2)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Designing a 2048-Chiplet, 14336-Core Waferscale Processor
- DOI:10.1109/dac18074.2021.9586194
- 发表时间:2021-12
- 期刊:
- 影响因子:0
- 作者:Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;S. Iyer;S. Pamarti;Rakesh Kumar;Puneet Gupta
- 通讯作者:Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;S. Iyer;S. Pamarti;Rakesh Kumar;Puneet Gupta
Chiplets: How Small is too Small?
Chiplet:多小才算太小?
- DOI:
- 发表时间:2023
- 期刊:
- 影响因子:0
- 作者:Graening A.;Pal S.;Gupta P.
- 通讯作者:Gupta P.
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