SHF: Small: Domain-Specific FPGAs to Accelerate Unrolled DNNs with Fine-Grained Unstructured Sparsity and Mixed Precision

人工智能（AI）已经成为我们日常生活中必不可少的一部分，它彻底改变了各个行业，并改变了我们与技术互动的方式。人工智能取得显著进步背后的关键因素之一是深度神经网络（dnn）的效率。这些复杂的系统，类似于人类的大脑，擅长处理大量的数据，使他们能够学习和做出明智的决定。与传统的计算机程序相比，深度神经网络在图像识别、自然语言处理和决策等任务中表现出优越的性能。不幸的是，这种改进的性能需要更多的能量和计算资源。这不仅增加了它们的运行成本，而且限制了它们在资源受限环境（如电池供电设备）中的部署，阻碍了人工智能系统的广泛采用。有趣的是，深度神经网络计算通常涉及许多冗余操作，通常称为“稀疏性”。该项目旨在开发专门的计算机芯片和软件程序，利用丰富的细粒度稀疏性来提高人工智能性能，同时降低能耗和计算成本。该研究奖项的成果将被整合到研究生和本科生的教育课程和研究指导计划中，以教育下一代计算机工程师关于硬件/软件协同设计对深度学习的重要性。此外，计划开展外展活动，以增加妇女对人工智能硬件开发的参与。该项目专注于具有细粒度非结构化稀疏性和混合精度的深度神经网络的硬件加速，这两种形式的冗余尚未被现有的计算机芯片有效地利用。研究团队专注于在可编程硬件上优化展开的DNN电路，从目前现场可编程门阵列（fpga）的通用硬件结构开始，向DNN优化结构发展。一个系统的基准驱动的方法被用来专门的FPGA组件展开DNN电路的实现。此外，该团队还研究了FPGA结构的更重大变化，例如时间复用和内存计算，以增加逻辑容量并能够部署更大的dnn。为了获得最大的效率，我们共同设计了DNN稀疏化算法，包括剪枝、量化和参数共享。该奖项有望产生新的位可编程硬件架构、深度神经网络稀疏化算法，以及协同设计稀疏深度神经网络和硬件的研究框架。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Artificial intelligence (AI) has become an essential part of our daily lives, revolutionizing various industries and transforming the way we interact with technology. One of the key factors behind AI's remarkable progress is the efficiency of deep neural networks (DNNs). These complex systems, akin to the human brain, excel at processing vast amounts of data, enabling them to learn and make informed decisions. Compared to traditional computer programs, DNNs have shown superior performance in tasks such as image recognition, natural language processing, and decision-making. Unfortunately, this improved performance requires substantially more energy and computational resources. This not only increases their running costs but also limits their deployment in resource-constrained environments like battery-powered devices, hindering the broader adoption of AI systems. Interestingly, DNN computations often involve many redundant operations, termed generally as "sparsity." This project aims to develop specialized computer chips and software programs that exploit abundant fine-grained sparsity to enhance AI performance while reducing energy consumption and computational costs. Outcomes of this research award will be integrated into educational curricula and research mentorship plans at the graduate and undergraduate level, to educate the next generation of computer engineers on the importance of hardware/software codesign for deep learning. In addition, an outreach activity is planned to increase the participation of women in the hardware development for AI.This project focuses on the hardware acceleration of DNNs with fine-grained unstructured sparsity and mixed precision, two forms of redundancy that have yet to be exploited efficiently by existing computer chips. The research team focuses on optimizing unrolled DNN circuits on programmable hardware, starting with the current general-purpose hardware fabric of field-programmable gate arrays (FPGAs) and progressing towards DNN-optimized fabrics. A systematic benchmark-driven approach is used to specialize FPGA components for the implementation of unrolled DNN circuits. Furthermore, the team investigates more significant changes to the FPGA fabric, such as time-multiplexing and in-memory computing, to increase logic capacity and enable the deployment of larger DNNs. To extract maximum efficiency, DNN sparsification algorithms are codesigned, including pruning, quantization, and parameter sharing. This award is expected to result in new bit-programmable hardware architectures, DNN sparsification algorithms, and a research framework to synergistically codesign sparse DNNs and hardware.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.