SHF: Small: Domain-Specific FPGAs to Accelerate Unrolled DNNs with Fine-Grained Unstructured Sparsity and Mixed Precision

SHF：小型：特定领域 FPGA 加速具有细粒度非结构化稀疏性和混合精度的展开 DNN

• 批准号: 2303626
• 负责人: Mohamed Abdelfattah
• 金额: $ 59.84万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-05-15 至 2026-04-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2303626&HistoricalAwards=false
• 关键词: SHF; Small; Domain; Specific; FPGAs

Artificial intelligence (AI) has become an essential part of our daily lives, revolutionizing various industries and transforming the way we interact with technology. One of the key factors behind AI's remarkable progress is the efficiency of deep neural networks (DNNs). These complex systems, akin to the human brain, excel at processing vast amounts of data, enabling them to learn and make informed decisions. Compared to traditional computer programs, DNNs have shown superior performance in tasks such as image recognition, natural language processing, and decision-making. Unfortunately, this improved performance requires substantially more energy and computational resources. This not only increases their running costs but also limits their deployment in resource-constrained environments like battery-powered devices, hindering the broader adoption of AI systems. Interestingly, DNN computations often involve many redundant operations, termed generally as "sparsity." This project aims to develop specialized computer chips and software programs that exploit abundant fine-grained sparsity to enhance AI performance while reducing energy consumption and computational costs. Outcomes of this research award will be integrated into educational curricula and research mentorship plans at the graduate and undergraduate level, to educate the next generation of computer engineers on the importance of hardware/software codesign for deep learning. In addition, an outreach activity is planned to increase the participation of women in the hardware development for AI.This project focuses on the hardware acceleration of DNNs with fine-grained unstructured sparsity and mixed precision, two forms of redundancy that have yet to be exploited efficiently by existing computer chips. The research team focuses on optimizing unrolled DNN circuits on programmable hardware, starting with the current general-purpose hardware fabric of field-programmable gate arrays (FPGAs) and progressing towards DNN-optimized fabrics. A systematic benchmark-driven approach is used to specialize FPGA components for the implementation of unrolled DNN circuits. Furthermore, the team investigates more significant changes to the FPGA fabric, such as time-multiplexing and in-memory computing, to increase logic capacity and enable the deployment of larger DNNs. To extract maximum efficiency, DNN sparsification algorithms are codesigned, including pruning, quantization, and parameter sharing. This award is expected to result in new bit-programmable hardware architectures, DNN sparsification algorithms, and a research framework to synergistically codesign sparse DNNs and hardware.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

人工智能（AI）已成为我们日常生活中必不可少的一部分，它彻底改变了各个行业，并改变了我们与技术互动的方式。人工智能取得显著进步的关键因素之一是深度神经网络（DNN）的效率。这些复杂的系统，类似于人类的大脑，擅长处理大量的数据，使他们能够学习和做出明智的决定。与传统的计算机程序相比，DNN在图像识别、自然语言处理和决策等任务中表现出了上级性能。不幸的是，这种改进的性能需要更多的能量和计算资源。这不仅增加了它们的运行成本，还限制了它们在电池供电设备等资源受限环境中的部署，阻碍了人工智能系统的广泛采用。有趣的是，DNN计算通常涉及许多冗余操作，通常称为“稀疏性”。“该项目旨在开发专门的计算机芯片和软件程序，利用丰富的细粒度稀疏性来提高AI性能，同时降低能耗和计算成本。该研究奖的成果将被整合到研究生和本科生的教育课程和研究导师计划中，以教育下一代计算机工程师关于硬件/软件协同设计对深度学习的重要性。此外，为了提高女性在人工智能硬件开发中的参与度，还计划开展一项外展活动。该项目的重点是对具有细粒度非结构化稀疏性和混合精度的DNN进行硬件加速，这两种冗余形式尚未被现有的计算机芯片有效利用。研究团队专注于优化可编程硬件上展开的DNN电路，从当前的现场可编程门阵列（FPGA）通用硬件结构开始，并朝着DNN优化结构发展。一个系统的基准驱动的方法是用来专门的FPGA组件的实施展开DNN电路。此外，该团队还研究了FPGA结构的更重大变化，例如时间复用和内存计算，以增加逻辑容量并实现更大DNN的部署。为了提取最大效率，DNN稀疏化算法被共同设计，包括修剪、量化和参数共享。该奖项预计将产生新的位可编程硬件架构，DNN稀疏算法，以及协同协同设计稀疏DNN和硬件的研究框架。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs

BRAMAC：用于 FPGA 上乘法累加的 BRAM 计算架构

• DOI: 10.1109/fccm57271.2023.00015
• 发表时间: 2023
• 期刊: Proceedings Annual IEEE Symposium on Field Programmable Custom Computing Machines
• 作者: Chen, Yuzong;Abdelfattah, Mohamed S.
• 通讯作者: Abdelfattah, Mohamed S.

M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs

• DOI: 10.1109/icfpt59805.2023.00013
• 发表时间: 2023-11
• 期刊: 2023 International Conference on Field Programmable Technology (ICFPT)
• 作者: Yuzong Chen;Jordan Dotzel;M. Abdelfattah