Energy-Efficient Broadband Spectrum Sensing in Real Time Based on a Frequency-Domain Analog Signal Processor

随着无线电子设备数量的持续增长，射频频谱是一种稀缺资源。为了最大限度地利用有限的频谱资源，时间和空间频谱共享在下一代无线网络中至关重要。实时频谱感知是实现动态频谱共享的关键技术。它可以在拥挤的频谱中即时识别可用频谱，并帮助网络动态调整工作参数，如发射功率、载波频率和调制格式。随着越来越多的应用继续占用毫米波频谱，将需要覆盖传统频谱拥塞频段和新的毫米波频段的宽带频谱感知。然而，由于高耗电的高速模数转换器(ADC)和数字信号处理(DSP)电路，扫描超过10 GHz的非常宽的频谱带宽是具有挑战性的。为了应对这些挑战，该项目将探索一种新型的基于硅的频域模拟信号处理器，该处理器与先进的信号处理算法共同设计。这项研究将是将一系列数字可编程片上元件中的频率相关相长干涉和相消干涉应用于频域模拟信号处理的第一个理论和实验研究。该项目的研究成果可被业界采用，使广泛的半导体和无线网络公司受益。该项目的成功还将帮助培养学生成为无线行业的创新工程师，从而保持美国在无线技术和半导体领域的持续领先地位。该项目的目标是开发一种基于硅的频域模拟信号处理器，与先进的信号处理算法共同设计，以实现节能(100 mW功耗)、宽带(25 GHz带宽)和低延迟(100 ns扫描时间)的频谱传感器。该设计基于一系列片上可编程色散工程元件中的频率相关的相长和相消干涉，以产生数字可调窄带通滤波器的频率响应。所提出的模拟处理器可以在保持恒定带宽的情况下，在较宽的频率范围内线性扫描“笔状”窄通带的中心频率，以进行频谱扫描。对于建议的模拟处理器的硅实现，将探索几个基本的IC和体系结构级别的创新设计，用于1)由多功能移相器和级联延迟单元组成的色散工程元件，2)用于减小芯片面积的可扩展路径共享延迟信号组合器，以及3)与先进的信号处理算法共同设计的数字控制电路，以协调色散工程元件，以在分辨率带宽、扫描范围、延迟和能效之间实现最佳平衡。提出的信号处理算法利用了压缩感知和分层分组测试的最新进展，并利用所提出的体系结构的可编程性来进一步提高感知性能。拟议的宽带、节能、低延迟频谱感知的成功开发将使动态频谱共享能够极大地缓解对有限无线电频谱的不断增长的需求，并最大限度地提高频谱利用率，从而使现代和未来无线网络的运营和管理发生革命性变化。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

RF spectrum is a scarce resource as the number of wireless electronic devices continues to explode. To maximize the utilization of the limited spectrum resource, temporal and spatial spectrum sharing is essential in next-generation wireless networks. Real-time spectrum sensing is a crucial technology to enable dynamic spectrum sharing. It identifies available spectrum instantaneously in the crowded frequency spectrum and helps the networks to dynamically adapt operating parameters such as transmit power, carrier frequency, and modulation format. As more applications continue to occupy millimeter-wave (mm-wave) spectrum, broadband spectrum sensing which covers both traditionally spectrum-congested frequency bands and new mm-wave bands will be needed. However, scanning a very broad spectrum bandwidth of more than 10 GHz is challenging due to the power-hungry high-speed analog-to-digital converter (ADC) and digital signal processing (DSP) circuitry. To address these challenges, this project will explore a novel silicon-based frequency domain analog signal processor co-designed with advanced signal processing algorithms. The research will be the first theoretical and experimental study of applying frequency-dependent constructive and destructive interference in an array of digitally programmable on-chip elements to frequency-domain analog signal processing. The research outcomes from this project can be adopted by industry to benefit a wide range of semiconductor and wireless network companies. The success of the project will also help maintain the continuous leadership of the United States in wireless technologies and semiconductors by training students to be innovative engineers in wireless industry.The goal of this project is to develop a silicon-based frequency domain analog signal processor co-designed with advanced signal processing algorithms to realize an energy-efficient ( 100 mW power consumption), broadband (25 GHz bandwidth), and low-latency (100 ns scan time) spectrum sensor. The design is based on frequency-dependent constructive and destructive interference in an array of on-chip programmable dispersion-engineered elements to create the frequency response of a digitally tunable narrow-bandpass filter. The proposed analog processor can sweep the center frequency of a "pencil-like" narrow passband linearly over a wide frequency range for spectrum scanning while maintaining a constant bandwidth. For the silicon implementation of the proposed analog processor, several fundamental IC and architecture-level innovations will be explored for the design of 1) a dispersion-engineered element that consists of a multi-functional phase shifter and cascaded delay cells, 2) a scalable path-sharing delayed signal combiner for chip area reduction, and 3) a digital control circuitry co-designed with advanced signal processing algorithms to orchestrate the dispersion-engineered elements for the optimal trade-off among resolution bandwidth, scan range, latency, and energy efficiency. The proposed signal processing algorithms leverage the recent advances in compressive sensing and hierarchical group testing and utilize the programmability of the proposed architecture to improve the sensing performance further. The successful development of the proposed broadband, energy-efficient, low-latency spectrum sensing will enable dynamic spectrum sharing to revolutionize the operation and management of modern and future wireless networks by dramatically alleviating the constantly increasing demands of the limited radio spectrum and maximizing utilization of the spectrum.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.