CAREER: Next Generation of High-Level Synthesis for Agile Architectural Design (ArchHLS)

在计算领域，对创新硬件架构的需求不断增长，推动了计算机架构的进步。然而，传统的寄存器传输级（RTL）设计方法是耗时和劳动密集型。该项目旨在促进更广泛地采用高级综合（HLS）工具，以显着减少设计时间，特别是对于一般的建筑设计。HLS工具使更高层次的编程和自动综合，但其应用在全面的计算机体系结构研究仍然有限。该项目的意义在于通过从根本上创新HLS工具来促进敏捷硬件开发，克服寄存器传输级的生产力挑战，并释放HLS在不同计算领域更广泛应用的潜力。开发的工具链将通过组织教程、研讨会和演示活动公开提供给更多用户。该研究将被纳入教育计划，包括对本科生和硕士生的研究培训，包括在线学生，从代表性不足的群体中招募和保留学生，课程开发以及与工业界共同举办的创新国际设计竞赛。该项目旨在通过引入下一代工具ArchHLS，应对两大研究挑战。首先，HLS工具在将特定算法合成为硬件方面具有上级优势，但对于一般的特定领域架构设计能力有限。其次，设计具有兼容编译器的通用架构以及自动改进底层架构以适应不断变化的工作负载是具有挑战性的。为了应对这些挑战，ArchHLS通过三项关键创新来促进敏捷硬件开发。首先，ArchHLS简化了架构设计和工作负载映射，允许灵活的架构提取和自定义控制流。其次，ArchHLS通过自动化工作负载编译、映射和计算模式匹配来自动化架构演化，以适应快速变化的算法。第三，ArchHLS能够为设计提供全面准确的性能分析，为架构演进提供反馈。除了推进电子设计自动化（EDA）工具之外，这项研究还具有更广泛的社会影响，符合可持续计算和可持续计算的宏伟愿景，例如气候建模和科学计算。工具链的公开可用性促进了研究传播、教育整合和包容性工作，旨在使不同的社区受益，并促进高效的算法/架构协同设计。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

In the landscape of computing, the demand for innovative hardware architectures is ever-growing, driving advancements in computer architecture. However, the conventional Register Transfer Level (RTL) design approach is time-consuming and labor-intensive. This project aims to facilitate the broader adoption of High-Level Synthesis (HLS) tools to significantly reduce design time, particularly for general architectural design. HLS tools enable higher-level programming and automatic synthesis, yet their application in comprehensive computer architecture studies remains limited. The significance of this project lies in promoting agile hardware development by fundamentally innovating HLS tools, overcoming the productivity challenges at the register transfer level, and unlocking the potential for more widespread application of HLS in diverse computing domains. The developed tool chain will be publicly available and exposed to more users by organizing tutorials, workshops, and demo events. The research will be integrated into education programs with activities on research training for undergraduate and master students, including online students, recruitment and retention of students from underrepresented groups, curriculum development, and innovative international design competitions co-hosted with industry.This project aims to revolutionize High-Level Synthesis (HLS) tools by introducing a next-generation tool, ArchHLS, addressing two major research challenges. First, HLS tools are superior in synthesizing a specific algorithm into hardware but have limited capability for general domain-specific architecture designs. Second, it is challenging to design general architectures with compatible compilers and to automatically improve the underlying architecture for evolving workloads. To address these challenges, ArchHLS facilitates agile hardware development by making three key innovations. First, ArchHLS decouples architectural design and workload mapping, allowing flexible architecture extraction and customized control flow. Second, ArchHLS automates architecture evolution to adapt to fast-changing algorithms via automated workload compilation, mapping, and computation pattern matching. Third, ArchHLS enables comprehensive and accurate performance profiling for designs to provide feedback for architecture evolution. Beyond advancing Electronic Design Automation (EDA) tooling, this research has broader societal implications, aligning with the grand vision of sustainability for computing and computing for sustainability, such as climate modeling and scientific computing. The public availability of the toolchain fosters research dissemination, educational integration, and inclusivity efforts, aiming to benefit diverse communities and promote efficient algorithm/architecture co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.