Quantification of the Trade-off between Energy and Exactness in Computer Vision Processor Architectures Enhanced with Stochastic Computing Mechanisms

考虑到许多应用的能力（例如，计算机视觉）以容忍计算结果中的精度损失。设计人员可以放松实施约束并故意暴露硬件可变性，而不是针对具有昂贵保护频带的最坏情况场景设计硬件，从而获得显著的处理性能改进和能源效益。典型的实施约束与操作频率或操作电压有关。降低操作电压将显著降低功耗并增加错误率（即，故障）。如何设计“不精确”的硬件系统，以降低错误率，同时暴露硬件的可变性，是随机计算的主要挑战。理解所有这些硬件设计权衡及其对目标应用的影响是强制性的，因为计算不精确。在处理器架构和计算机视觉应用中使用随机计算需要研究所有设计级别的新硬件设计技术（即，应用、处理器架构和芯片布局）。该项目提出量化计算机视觉处理器架构中的能量-精确度权衡，并通过随机计算机制进行增强。为此目的，两种不同的处理器架构（即，一个VLIW体系结构增强与SIMD指令和向量处理器体系结构），正交开发的数据并行固有的计算机视觉算法将被研究。不同的处理特性导致不同的硬件机制，其需要不同的随机计算方法以提高其性能和/或能量效率。分析误差和功率模型的随机计算机制将分别得出估计的计算精度和功耗的处理器架构。此外，基于FPGA的快速原型将用于加速两种处理器架构的处理性能的验证和分析。此外，随机机制和功耗模型引入的计算误差，考虑到内部开关活动，也将被仿真。几个不同的质量，可靠性和成本效益的目标检测和跟踪的特征提取算法将被用来评估随机计算误差的影响。最后，该项目将不仅允许找到和理解的最佳随机处理器架构的示例性特征提取算法，而且还确定新的随机计算机制，特别是适合于计算机视觉应用的不同处理器架构类型。

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits. Typical implementation constraints are related to operation frequency or operation voltage. Reducing the operation voltage will significantly reduce the power consumption and increase the error rate (i.e., malfunctioning). How to design "imprecise" hardware systems, in order to reduce the error rate while exposing hardware variability, is the main challenge of stochastic computing. Understanding all these hardware design trade-offs and their implication on the target application resulting from the imprecise computation is mandatory.The use of stochastic computing in processor architectures and computer vision applications requires the study of new hardware design techniques at all design levels (i.e., application, processor architecture, and chip layout). This project proposes to quantify the energy-exactness trade-offs in computer vision processor architectures enhanced with stochastic computing mechanisms. For this purpose, two different processor architectures (i.e., a VLIW architecture enhanced with SIMD instructions and a Vector Processor architecture), which orthogonally exploit the data parallelism inherent in computer vision algorithms will be studied. Different processing characteristics result in different hardware mechanisms that require different stochastic computing approaches in order to increase their performance and/or energy efficiency. Analytical error and power models of the resulting stochastic computing mechanisms will be derived to estimate the computation exactness and power consumption of both processor architectures, respectively. Moreover, FPGA-based rapid prototyping will be used to accelerate the verification and analysis of the processing performance of both processor architectures. Furthermore, the computation errors introduced by the stochastic mechanisms and the power consumption models, taking the internal switching activity into account, will be also emulated. Several feature extraction algorithms with different quality, reliability, and cost-effectiveness for object detection and tracking will be used to evaluate the influence of the stochastic computing errors. Finally, this project will allow not only to find and understand the optimal stochastic processor architecture for the exemplary feature extraction algorithm, but also to identify new stochastic computing mechanisms for different processor architecture types especially suited for computer vision applications.