Quantification of the Trade-off between Energy and Exactness in Computer Vision Processor Architectures Enhanced with Stochastic Computing Mechanisms

随机计算最近成为设计节能嵌入式硬件系统的一种有前途的方法，考虑到许多应用程序（例如，计算机视觉）容忍计算结果精度损失的能力。设计人员可以放松实现约束并故意暴露硬件可变性，而不是为具有昂贵保护带的最坏情况设计硬件，从而获得显著的处理性能改进和能源效益。典型的实现约束与操作频率或操作电压有关。降低工作电压将显著降低功耗，并增加错误率（即故障）。如何设计“不精确”的硬件系统，以降低错误率，同时暴露硬件的可变性，是随机计算的主要挑战。必须理解所有这些硬件设计权衡以及它们对目标应用程序的影响，这些影响是由不精确的计算引起的。在处理器架构和计算机视觉应用中使用随机计算需要在所有设计层面（即应用程序，处理器架构和芯片布局）研究新的硬件设计技术。本项目旨在量化随机计算机制增强的计算机视觉处理器体系结构中的能量精度权衡。为此，将研究两种不同的处理器体系结构（即，用SIMD指令增强的VLIW体系结构和矢量处理器体系结构），它们正交地利用计算机视觉算法固有的数据并行性。不同的处理特性导致不同的硬件机制，需要不同的随机计算方法来提高它们的性能和/或能源效率。本文将推导出随机计算机制的分析误差和功耗模型，分别用于估计两种处理器架构的计算精度和功耗。此外，基于fpga的快速原型将用于加速验证和分析两种处理器架构的处理性能。此外，还将模拟考虑内部开关活动的随机机制和功耗模型所引入的计算误差。在目标检测和跟踪中，将使用几种具有不同质量、可靠性和成本效益的特征提取算法来评估随机计算误差的影响。最后，这个项目不仅可以找到和理解典型特征提取算法的最佳随机处理器架构，还可以为不同的处理器架构类型确定新的随机计算机制，特别是适合计算机视觉应用。

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits. Typical implementation constraints are related to operation frequency or operation voltage. Reducing the operation voltage will significantly reduce the power consumption and increase the error rate (i.e., malfunctioning). How to design "imprecise" hardware systems, in order to reduce the error rate while exposing hardware variability, is the main challenge of stochastic computing. Understanding all these hardware design trade-offs and their implication on the target application resulting from the imprecise computation is mandatory.The use of stochastic computing in processor architectures and computer vision applications requires the study of new hardware design techniques at all design levels (i.e., application, processor architecture, and chip layout). This project proposes to quantify the energy-exactness trade-offs in computer vision processor architectures enhanced with stochastic computing mechanisms. For this purpose, two different processor architectures (i.e., a VLIW architecture enhanced with SIMD instructions and a Vector Processor architecture), which orthogonally exploit the data parallelism inherent in computer vision algorithms will be studied. Different processing characteristics result in different hardware mechanisms that require different stochastic computing approaches in order to increase their performance and/or energy efficiency. Analytical error and power models of the resulting stochastic computing mechanisms will be derived to estimate the computation exactness and power consumption of both processor architectures, respectively. Moreover, FPGA-based rapid prototyping will be used to accelerate the verification and analysis of the processing performance of both processor architectures. Furthermore, the computation errors introduced by the stochastic mechanisms and the power consumption models, taking the internal switching activity into account, will be also emulated. Several feature extraction algorithms with different quality, reliability, and cost-effectiveness for object detection and tracking will be used to evaluate the influence of the stochastic computing errors. Finally, this project will allow not only to find and understand the optimal stochastic processor architecture for the exemplary feature extraction algorithm, but also to identify new stochastic computing mechanisms for different processor architecture types especially suited for computer vision applications.