权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Quantification of the Trade-off between Energy and Exactness in Computer Vision Processor Architectures Enhanced with Stochastic Computing Mechanisms

通过随机计算机制增强的计算机视觉处理器架构中能量与精确性之间权衡的量化

基本信息

批准号：
279180031
负责人：
Professor Dr.-Ing. Holger Blume
金额：
--
依托单位：
Abteilung Entwurf integrierter Systeme
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2015
资助国家：
德国
起止时间：
2014-12-31 至 2018-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/279180031?language=en
关键词：
Quantification Trade off between Energy

项目摘要

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits. Typical implementation constraints are related to operation frequency or operation voltage. Reducing the operation voltage will significantly reduce the power consumption and increase the error rate (i.e., malfunctioning). How to design "imprecise" hardware systems, in order to reduce the error rate while exposing hardware variability, is the main challenge of stochastic computing. Understanding all these hardware design trade-offs and their implication on the target application resulting from the imprecise computation is mandatory.The use of stochastic computing in processor architectures and computer vision applications requires the study of new hardware design techniques at all design levels (i.e., application, processor architecture, and chip layout). This project proposes to quantify the energy-exactness trade-offs in computer vision processor architectures enhanced with stochastic computing mechanisms. For this purpose, two different processor architectures (i.e., a VLIW architecture enhanced with SIMD instructions and a Vector Processor architecture), which orthogonally exploit the data parallelism inherent in computer vision algorithms will be studied. Different processing characteristics result in different hardware mechanisms that require different stochastic computing approaches in order to increase their performance and/or energy efficiency. Analytical error and power models of the resulting stochastic computing mechanisms will be derived to estimate the computation exactness and power consumption of both processor architectures, respectively. Moreover, FPGA-based rapid prototyping will be used to accelerate the verification and analysis of the processing performance of both processor architectures. Furthermore, the computation errors introduced by the stochastic mechanisms and the power consumption models, taking the internal switching activity into account, will be also emulated. Several feature extraction algorithms with different quality, reliability, and cost-effectiveness for object detection and tracking will be used to evaluate the influence of the stochastic computing errors. Finally, this project will allow not only to find and understand the optimal stochastic processor architecture for the exemplary feature extraction algorithm, but also to identify new stochastic computing mechanisms for different processor architecture types especially suited for computer vision applications.

考虑到许多应用程序(例如计算机视觉)容忍计算结果中的精度损失的能力，随机计算最近已经成为设计节能嵌入式硬件系统的一种很有前途的方法。设计人员无需为具有昂贵保护带的最坏情况设计硬件，而是可以放松实施限制并刻意暴露硬件的可变性，从而获得显著的处理性能改进和能源效益。典型的实现约束与操作频率或操作电压有关。降低操作电压将显著降低功耗并增加错误率(即故障)。如何设计不精确的硬件系统，以便在暴露硬件易变性的同时降低错误率，是随机计算面临的主要挑战。在处理器体系结构和计算机视觉应用中使用随机计算需要在所有设计级别(即应用、处理器体系结构和芯片布局)研究新的硬件设计技术。这个项目建议量化计算机视觉处理器架构中的能量-精确度权衡，以增强随机计算机制。为此，将研究两种不同的处理器体系结构(即，用SIMD指令增强的VLIW体系结构和矢量处理器体系结构)，它们正交地利用计算机视觉算法固有的数据并行性。不同的处理特性导致需要不同的随机计算方法以提高其性能和/或能量效率的不同的硬件机制。推导出随机计算机制的分析误差和功耗模型，以分别估计两种处理器体系结构的计算精度和功耗。此外，还将使用基于现场可编程门阵列的快速原型技术来加速验证和分析两种处理器架构的处理性能。此外，还将对随机机制和考虑内部开关活动的功耗模型引入的计算误差进行仿真。为了评估随机计算误差的影响，将使用几种不同质量、可靠性和成本效益的特征提取算法来进行目标检测和跟踪。最后，该项目将不仅允许找到和理解用于示例性特征提取算法的最优随机处理器体系结构，而且还将为特别适合于计算机视觉应用的不同处理器体系结构类型识别新的随机计算机制。

项目成果

期刊论文数量（5）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

A Coding Approach to Improve the Energy Efficiency of Approximate NoCs

DOI：
10.1109/recosoc48741.2019.9034965
发表时间：
2019-07
期刊：
2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
影响因子：
0
作者：
A. Najafi;Lennart Bamberg;G. P. Vayá;A. Ortiz
通讯作者：
A. Najafi;Lennart Bamberg;G. P. Vayá;A. Ortiz

Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder

DOI：
10.1109/tvlsi.2018.2822278
发表时间：
2018-04
期刊：
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
影响因子：
2.8
作者：
Ayad M. Dalloo;Ardalan Najafi;Alberto García-Ortiz
通讯作者：
Ayad M. Dalloo;Ardalan Najafi;Alberto García-Ortiz

Misalignment-aware delay modeling of narrow on-chip interconnects considering variability

考虑可变性的窄片上互连的未对准感知延迟建模

DOI：
10.1109/mocast.2018.8376593
发表时间：
2018
期刊：
2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)
影响因子：
0
作者：
A. Najafi;L. Bamberg;A. Garcia-Ortiz
通讯作者：
A. Garcia-Ortiz

FPGA emulation methodology for fast and accurate power estimation of embedded processors

用于快速准确估计嵌入式处理器功耗的 FPGA 仿真方法