REDOX: Decrease of simulation- and radiation-time of rad-hard circuits by optimizing of SET models

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The main goal of the running REDOX project is to establish a unified framework for optimized and accurate characterization of Single Event Transient (SET) effects at the circuit level. This will help in reducing the need for extensive device simulations and irradiation experiments, and facilitate the effective development of novel rad-hard CMOS and BiCMOS libraries. To accomplish this goal, it is required to better understand the impact of all relevant irradiation, design, technological and operating parameters on the SET generation and propagation within the combinational logic, and its latching into the sequential logic.In the approved first part of the project we have investigated the SET effects in standard and non-standard logic gates, employing SPICE simulations for 250, 130 and 65 nm CMOS technologies, and TCAD simulations for 250 nm technology. The main achievement in the first phase is the establishment of two analytical models for predicting the SET robustness of standard and non-standard logic gates. In addition, we have gained substantial insight into the physical mechanisms of SET effects and the impact of irradiation, design and operating parameters on the formation of SET current and voltage pulses. Also, we have conducted detailed analysis of advanced techniques for experimental characterization of SET effects, and a first test chip for SET pulse width measurement has been designed and manufactured in IHP’s 250 nm bulk CMOS process. Based on the results achieved in the first 18 months of the project, we have several papers.We believe that the requested extension of the project would allow for a full accomplishment of the originally proposed objectives. To achieve the proposed objectives, the planned research will be focused on: (1) further improvement of the SET robustness models derived in the first phase of the project, (2) use of the acquired knowledge on SET effects to enhance existing SET current, SET voltage and SET propagation models, and (3) integration of the improved SET models into a coherent SET evaluation framework. The SET models and the complete characterization framework will be tested on selected benchmark circuits using SPICE simulations and irradiation experiments. In addition, with respect to the current state-of-the-art, we would like to slightly extend the scope of our work by addressing additional important issues which have not been addressed in the first version of the project.