Study on poly-Si junctionless nanowire transistors

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In this works, we successfully implemented high performance GAA poly-Si JL NW transistors especially with ideal SS characteristics even in poly-Si based transistor with high density of trapping states at grain boundaries. In addition, relatively small VT variability characteristic was achieved even in JL structure which usually suffer from severe random dopant fluctuation due to high channel concentration. These achievements are mainly originated from the high quality of poly-Si channel by improved fabrication processes including B segregation and F passivation effects.