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Ensuring Robustness in Low-Power Asynchronous Circuits - ENROL

确保低功耗异步电路的鲁棒性 - ENROLL

基本信息

批准号：
389059471
负责人：
Professor Dr.-Ing. Milos Krstic
金额：
--
依托单位：
Institut für Technische Informatik
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2018
资助国家：
德国
起止时间：
2017-12-31 至 2021-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/389059471?language=en
关键词：
Ensuring Robustness Low Power Asynchronous

项目摘要

Currently, virtually all reasonably complex digital circuits, such as microprocessors, have all their internal operational sequences controlled by a rigid clock, i.e. these circuits operate synchronous. An alternative design paradigm, namely asynchronous design, when suitably optimized, offers the potential for realizing the same functionality with higher energy efficiency, higher performance and higher robustness. The project ENROL is dedicated to the latter aspect, namely the question how far asynchronous designs are indeed more robust than synchronous ones, in terms of being more tolerant to external interferences or sub-optimal operating conditions. To this end, in a first step a formal model shall be elaborated for the fault-free behavior of asynchronous circuits designed following the most relevant existing asynchronous approaches. In a next step all possible fault effects shall be expressed in that model, classified and associated with their respective probabilities. For those faults that turn out to be finally tolerated, the mechanisms underlying this tolerance shall be explored. The results thus obtained shall be compared with those for comparable synchronous circuits to give evidence for the hypothesized higher robustness of asynchronous circuits; the differences shall be quantified by means of suitable metrics. In this process, theoretical considerations will be accompanied by comprehensive simulation studies and experimental measurements for circuits whose design is part of the project as well.Based on the thorough understanding of the fault effects and the inherent fault tolerance mechanisms, well directed modifications to and extensions of the asynchronous circuits and concepts can be devised to further enhance their robustness. Here, the available concepts range from technological enhancements (transistor geometry and placement) over changes in the circuit towards coding methods. While fault-tolerance approaches for asynchronous designs do exist in the literature already, the systematic treatment of the topic from modelling to experiment, covering all relevant design asynchronous design paradigms, and directly comparing all alternatives, clearly represents a contribution to the state of the art.The results of ENROL will allow to give evidence for and to better leverage the robustness benefits of asynchronous design. This could make the latter more attractive for critical applications where designers would as well appreciate the other advantages like energy efficiency or higher performance. So on the long run ENROL will contribute to constructing fast and energy-efficient computers that yet work reliable under faults and sub-optimal conditions.

目前，几乎所有相当复杂的数字电路，例如微处理器，其所有内部操作序列都由刚性时钟控制，即这些电路同步操作。另一种设计范例，即异步设计，如果得到适当的优化，就有可能以更高的能效、更高的性能和更高的健壮性来实现相同的功能。Enrol项目致力于后一个方面，即在对外部干扰或次优操作条件的容忍度方面，异步设计确实比同步设计更健壮。为此，在第一步中，应详细说明按照最相关的现有异步方法设计的异步电路的无故障行为的正式模型。在下一步中，所有可能的故障影响将在该模型中表达、分类并与其各自的概率相关联。对于那些最终被容忍的错误，应该探索这种容忍背后的机制。这样得到的结果应与可比较的同步电路的结果进行比较，以证明异步电路假设的更高的稳健性；差异应通过适当的度量来量化。在这一过程中，将伴随着对设计也是项目一部分的电路进行全面的仿真研究和实验测量，在深入了解故障影响和内在容错机制的基础上，可以对异步电路和概念进行有针对性的修改和扩展，以进一步增强其健壮性。在这里，可用的概念范围从技术增强(晶体管几何形状和布局)到电路中的变化到编码方法。虽然文献中确实存在用于异步设计的容错方法，但从建模到实验的系统处理，涵盖所有相关的设计异步设计范例，并直接比较所有备选方案，显然是对技术状态的贡献。这可能会使后者对关键应用更具吸引力，在这些应用中，设计人员也会欣赏其他优势，如能效或更高的性能。因此，从长远来看，Enrol将有助于构建快速和节能的计算机，这些计算机在故障和次优条件下仍能可靠地工作。

项目成果

期刊论文数量（4）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template

刀片模板异步控制器的面向测试设计和布局生成

DOI：
10.1109/async49171.2020.00021
发表时间：
2020
期刊：
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
影响因子：
0
作者：
F. A. Kuentzer;L. R. Juracy;M. T. Moreira;A. M. Amory
通讯作者：
A. M. Amory

Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs

用于异步捆绑数据设计的软错误检测和纠正架构

DOI：
10.1109/tcsi.2020.2998911
发表时间：
2020
期刊：
IEEE Transactions on Circuits and Systems I: Regular Papers
影响因子：
0
作者：
F. A. Kuentzer;M. Krstic
通讯作者：
M. Krstic

Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures

用于软错误弹性异步架构的抗辐射点击控制器

DOI：
10.1109/async49171.2020.00020
发表时间：
2020
期刊：
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
影响因子：
0
作者：
F. A. Kuentzer;M. Herrera;O. Schrape;P. A. Beerel;M. Krstic
通讯作者：
M. Krstic

Testing the blade resilient asynchronous template

测试刀片弹性异步模板