Delta-Sigma-ADC with dynamic clock control

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The objective of the project is to provide new methods for dynamic variation of the sampling rate in Delta-Sigma ADCs. The control of the clock rate is to be performed digitally by evaluating the data stream and thus varying the clock generator. As far as possible, the data stream at the output of the chain of decimation and FIR filters is not evaluated, but rather the data stream from a clock plane between the clock of the Delta-Sigma modulator and the output data rate of the decimation filter. This method will help to minimize the temporal error of the decimated signal compared to the original signal when the modulator clock rate is changed.In a first step, various approaches for active digital clock control at model level are examined and the results are compared with those of asynchronous Delta-Sigma ADCs based on comparators with hysteresis. In addition to the signal quality, a criterion here is also the achievable reduction of the average clock frequency and thus the energy savings potential.The proposed solutions are to be verified on a modular and flexibly configurable system of analog test chip and digital signal processing on the FPGA. The core of the analog test chip will be a time-continuous Delta Sigma modulator with dynamic time scaling of the loop filter. For the time scaling, the resistors of the active RC integrators are programmable and the on resistances of the switches are calibrated.Despite a variable modulator clock, the output data rate is kept constant with a decimation filterproviding a variable down-sampling ratio. This filter is implemented together with the digital clock control on the FPGA.During the evaluation of the test chip and the evaluation of the results, a special attention is placed on possible deviations compared to the original model and to bring the actual measurements into line with the model. This ensures that all effects which lead to deviations from the ideal characteristic are understood well.