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Delta-Sigma-ADC with dynamic clock control

具有动态时钟控制的 Delta-Sigma ADC

基本信息

批准号：
391630368
负责人：
Professor Dr.-Ing. Dirk Killat
金额：
--
依托单位：
Lehrstuhl Mikroelektronik
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2017
资助国家：
德国
起止时间：
2016-12-31 至 2021-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/391630368?language=en
关键词：
Delta Sigma ADC dynamic clock

项目摘要

The objective of the project is to provide new methods for dynamic variation of the sampling rate in Delta-Sigma ADCs. The control of the clock rate is to be performed digitally by evaluating the data stream and thus varying the clock generator. As far as possible, the data stream at the output of the chain of decimation and FIR filters is not evaluated, but rather the data stream from a clock plane between the clock of the Delta-Sigma modulator and the output data rate of the decimation filter. This method will help to minimize the temporal error of the decimated signal compared to the original signal when the modulator clock rate is changed.In a first step, various approaches for active digital clock control at model level are examined and the results are compared with those of asynchronous Delta-Sigma ADCs based on comparators with hysteresis. In addition to the signal quality, a criterion here is also the achievable reduction of the average clock frequency and thus the energy savings potential.The proposed solutions are to be verified on a modular and flexibly configurable system of analog test chip and digital signal processing on the FPGA. The core of the analog test chip will be a time-continuous Delta Sigma modulator with dynamic time scaling of the loop filter. For the time scaling, the resistors of the active RC integrators are programmable and the on resistances of the switches are calibrated.Despite a variable modulator clock, the output data rate is kept constant with a decimation filterproviding a variable down-sampling ratio. This filter is implemented together with the digital clock control on the FPGA.During the evaluation of the test chip and the evaluation of the results, a special attention is placed on possible deviations compared to the original model and to bring the actual measurements into line with the model. This ensures that all effects which lead to deviations from the ideal characteristic are understood well.

该项目的目标是为 Delta-Sigma ADC 中采样率的动态变化提供新方法。时钟速率的控制将通过评估数据流并从而改变时钟发生器来以数字方式执行。尽可能不评估抽取和 FIR 滤波器链输出处的数据流，而是评估来自 Delta-Sigma 调制器的时钟与抽取滤波器的输出数据速率之间的时钟平面的数据流。当调制器时钟速率改变时，该方法将有助于最大限度地减少抽取信号与原始信号相比的时间误差。第一步，检查模型级有源数字时钟控制的各种方法，并将结果与基于迟滞比较器的异步 Delta-Sigma ADC 的结果进行比较。除了信号质量之外，这里的一个标准也是平均时钟频率的可实现降低，从而实现节能潜力。所提出的解决方案将在由模拟测试芯片和 FPGA 上的数字信号处理组成的模块化且可灵活配置的系统上进行验证。模拟测试芯片的核心将是一个时间连续的 Delta Sigma 调制器，具有环路滤波器的动态时间缩放功能。对于时间缩放，有源 RC 积分器的电阻器是可编程的，并且开关的导通电阻是校准的。尽管调制器时钟可变，但输出数据速率通过提供可变下采样比的抽取滤波器保持恒定。该滤波器与FPGA上的数字时钟控制一起实现。在评估测试芯片和评估结果的过程中，特别注意与原始模型相比可能存在的偏差，并使实际测量结果与模型保持一致。这确保了能够很好地理解导致偏离理想特性的所有影响。