Active and continuous compensation of clock jitter in continuous time Delta-Sigma ADCs

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Time-continuous delta-sigma ADCs are affected by clock jitter because the clock edges control the pulse width of the DAC and thus directly disturb the feedback signal. To reduce the influence of the clock jitter today mainly switched capacitors, also in conjunction with resistors (SCR-DAC), or multi-bit DACs are used. The disadvantage are higher slew rate requirements respectively a higher circuit complexity. Another proposal is based on an SC integrator, which compares a reference charge with a reference current integrated over the clock period and derives therefrom a correction signal for the jitter compensation. Critical here is the kT/C-noise and the charge injection compared to the small absolute value of the clock jitter. Moreover, the method is based on a switched capacitance, which is actually undesirable in continuous time delta-sigma ADC.In the project, a continuous-time compensation of the influence of the clock jitter in continuous-time delta-sigma ADCs with an active method is to be researched and realized. The principle is based on alternately up and down integration of the DAC reference and comparison of the integrated values over several clock periods. Based on the comparison, a correction signal is to be generated, which is fed into the integrator in subsequent clock phases and thus compensates for the error from the clock jitter. The advantage of this method is the successive continuous-time integration over the clock periods and thus a lower sensitivity to kT/C-noise and charge injection in the compensation circuit. Only with a compensation circuit, which itself is not subject to significant interference and noise, active compensation of the clock jitter can work.