Active and continuous compensation of clock jitter in continuous time Delta-Sigma ADCs

连续时间 Delta-Sigma ADC 中时钟抖动的主动和连续补偿

• 批准号: 444659113
• 负责人: Professor Dr.-Ing. Dirk Killat
• 金额: --
• 依托单位: Lehrstuhl Mikroelektronik
• 依托单位国家: 德国
• 项目类别: Research Grants
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/444659113?language=en
• 关键词: Active; continuous; compensation; clock; jitter

Time-continuous delta-sigma ADCs are affected by clock jitter because the clock edges control the pulse width of the DAC and thus directly disturb the feedback signal. To reduce the influence of the clock jitter today mainly switched capacitors, also in conjunction with resistors (SCR-DAC), or multi-bit DACs are used. The disadvantage are higher slew rate requirements respectively a higher circuit complexity. Another proposal is based on an SC integrator, which compares a reference charge with a reference current integrated over the clock period and derives therefrom a correction signal for the jitter compensation. Critical here is the kT/C-noise and the charge injection compared to the small absolute value of the clock jitter. Moreover, the method is based on a switched capacitance, which is actually undesirable in continuous time delta-sigma ADC.In the project, a continuous-time compensation of the influence of the clock jitter in continuous-time delta-sigma ADCs with an active method is to be researched and realized. The principle is based on alternately up and down integration of the DAC reference and comparison of the integrated values over several clock periods. Based on the comparison, a correction signal is to be generated, which is fed into the integrator in subsequent clock phases and thus compensates for the error from the clock jitter. The advantage of this method is the successive continuous-time integration over the clock periods and thus a lower sensitivity to kT/C-noise and charge injection in the compensation circuit. Only with a compensation circuit, which itself is not subject to significant interference and noise, active compensation of the clock jitter can work.

时间连续型Δ-Σ ADC会受到时钟抖动的影响，因为时钟边沿控制DAC的脉冲宽度，从而直接干扰反馈信号。为了减少时钟抖动的影响，目前主要使用开关电容，也可以结合电阻（SCR-DAC）或多位DAC。缺点是压摆率要求较高，电路复杂性较高。另一种建议是基于SC积分器，其将参考电荷与在时钟周期上积分的参考电流进行比较，并从中导出用于抖动补偿的校正信号。这里的关键是kT/C噪声和电荷注入与时钟抖动的小绝对值相比。此外，该方法是基于开关电容的，这在连续时间Δ-Σ ADC中是不可取的。本课题研究并实现了一种有源方法对连续时间Δ-Σ ADC中时钟抖动影响的连续时间补偿。其原理基于DAC基准电压源的交替上下积分以及几个时钟周期内积分值的比较。基于该比较，将产生校正信号，该校正信号在随后的时钟相位中被馈送到积分器中，并且因此补偿来自时钟抖动的误差。这种方法的优点是在时钟周期上连续的连续时间积分，因此对补偿电路中的kT/C噪声和电荷注入的灵敏度较低。只有使用补偿电路，其本身不受显著的干扰和噪声的影响，时钟抖动的主动补偿才能起作用。