Stretchable Multilayer Printed Circuit Boards: Fabrication, Surface Mount Challenge, Fundamental Research, and Applications

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BACKGROUND AND MOTIVATION: This proposal is at the cross-section of electronics technology and material science. It describes research to enable the realization of stretchable electronic assemblies. The team believes that many electronic system known today can be designed to morph to take on new shapes in the future. The most common technical approach is to use "monolithic" wafer scale processes to fabricate stretchable wavy electronics. While interesting, this proposal will follow a non-monolithic and more heterogeneous alternative. The proposed approach builds on a board level connection and assembly methodology which are open to devices from various sources with various dimensions. -SUPPORTING STUDIES: The points of entry for the investigators comes from prior research where the team has (i) learned to produce and process chip scale functional device segments and (ii) pioneering work on a unique placement and interconnection technology, which is based on fluidic self-assembly and transfer to enable the placement and interconnection of functional chip scale and microscopic device segments on unconventional substrates. The investigators gathered supporting results within the proposed field of research; the supporting results include the realization of (i) a stretchable and inflatable lighting structure, (ii) a microphone array which morphs into a sphere, and (iii) a spherical touchpad. -SUMMARY OF GAINED INSIGHTS: The supporting studies have shown that the bottlenecks are not the applications but a number of technical limitations and a lag of understanding of system level failure modes, which we propose to study and overcome in this proposal. -The FIRST GOAL and challenge addresses the fact that the research has been limited to designs with a single metallization layer; the fabrication of stretchable multiple metallization layers with vias in between, is presently not possible. This puts constraints on the routing and complexity of the systems that can be produced. Moreover, AC and HF properties have not been studid, which is another important task.-The SECOND GOAL and challenge deals with the assembly and electrical connection of active devices. Potential solutions are proposed to enable the assembly of not only macroscopic but also microscopic chips. New knowledge on component-size dependent scaling-laws concerning mechanical and electrical failure will be generated.-The THIRD GOAL and challenge deals with the study of system level failure types. Several critical regions have been identified. Failure mechanisms and a deeper understanding using computational models need to be derived. Computational guided designs and design rules are to be established.-The gained knowledge will be applied consecutively and suitable demonstrators are proposed. The proposed demonstrators include a metamorphic patch antenna, a spherical touch pad, as well as an active matrix LED array. The complexity increases from one year to the next.