Optimization of Multipliers for Reconfigurable Logic

本研究项目的目标是开发用于现场可编程门阵列（FPGA）上的资源和功率高效乘法器设计的算法。乘法属于最基本的算术运算，无论是本身还是作为高阶算术（如除法或函数逼近）的基本构建块。尽管乘法的实现自20世纪50年代以来一直在研究和改进，现场可编程门阵列作为一种重要的实现平台的出现要求FPGA的新概念，即一种体系结构-为了节约资源和提高效率，适应性的实现势在必行。应用范围从非常小的字大小（例如，用于神经网络）到非常大的单词大小（例如密码学应用）。拟议的工作将调查如何大范围的相关乘法，范围从2位到几百位的字长，为此，将优化它们由较小乘法器组成的组合以及小规模和大规模的基于逻辑的和嵌入式乘法器的组合。另外，由于放宽了精度限制，可能降低成本的潜力将基于截断和近似乘法方案进行探索。为了以通用的方式解决这些问题，应根据最近提出的乘数平铺概念制定一个统一的框架。

The goal of this research project is the development of algorithms for the design of resource and power efficient multipliers on field-programmable gate arrays (FPGAs). Multiplications belong to the most fundamental arithmetic operations either by themselves or as basic building blocks of higher-order arithmetic like divisions or function approximations.Even though the implementation of multiplications was investigated and improved since the 1950's, the advent of field-programmable gate arrays as an important implementation platform requires new conceptsas for FPGAs an architecture-adapted implementation is imperativefor resource savings and efficiency.Applications range from very small word sizes (e.g. used in neural networks) to very large word sizes (e.g. cryptographic applications).The proposed work will investigate how the large range of relevant multiplications, ranging from 2 bits to several hundred bits word size, can be efficiently implemented.For this, their composition out of smaller multipliers as well as the combination of logic-based and embedded multipliers at a small and large scale will be optimized.Additionally, the potential of possible cost reductions due to relaxed accuracy constraints will be explored based on truncation and approximate multiplication schemes.To tackle these problems in a common way, a unified framework shall be developed which is based on a multiplier tiling idea that was introduced recently.