Optimization of Multipliers for Reconfigurable Logic

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The goal of this research project is the development of algorithms for the design of resource and power efficient multipliers on field-programmable gate arrays (FPGAs). Multiplications belong to the most fundamental arithmetic operations either by themselves or as basic building blocks of higher-order arithmetic like divisions or function approximations.Even though the implementation of multiplications was investigated and improved since the 1950's, the advent of field-programmable gate arrays as an important implementation platform requires new conceptsas for FPGAs an architecture-adapted implementation is imperativefor resource savings and efficiency.Applications range from very small word sizes (e.g. used in neural networks) to very large word sizes (e.g. cryptographic applications).The proposed work will investigate how the large range of relevant multiplications, ranging from 2 bits to several hundred bits word size, can be efficiently implemented.For this, their composition out of smaller multipliers as well as the combination of logic-based and embedded multipliers at a small and large scale will be optimized.Additionally, the potential of possible cost reductions due to relaxed accuracy constraints will be explored based on truncation and approximate multiplication schemes.To tackle these problems in a common way, a unified framework shall be developed which is based on a multiplier tiling idea that was introduced recently.