Ultra-high Speed Global Interconnects for Inter-chip Communication

用于芯片间通信的超高速全局互连

基本信息

批准号：
15206041
负责人：
KIKKAWA Takamaro
金额：
$ 25.88万
依托单位：
HIROSHIMA UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2005
项目状态：
已结题

项目摘要

Ultra-wideband characteristics of Sierpinski carpet fractal antennas fabricated on silicon substrates with the resistivities of 2290 Ω-cm, 79.6 Ω-cm and 10 Ω-cm were investigated. The return losses lower than-10 dB and high transmission gains of approximately-14 dB were obtained for the antennas with 10 mm distance on the Si substrate with the resistivity of 2290 Ω-cm in the frequency range from 18 to 26.5 GHz. Gaussian monocycle pulses with 70 ps pulse width were transmitted in the Si substrates successfully and the corresponding voltage gains were-23 dB,-26 dB and-39 dB for the Si resistivities of 2290 Ω-cm, 79.6 Ω-cm and 10 Ω-cm, respectively.Ultra-wideband impulse based radio system uses Gaussian monocycle pulse as a transmitted signal at transmitting end and as a template signal at receiving end. In this paper we present a new fully integrated differential Gaussian monocycle pulse generator in 0.18 pm CMOS technology. Here the differential Gaussian monocycle pulse is generated from triangular shaped pulse by a single differentiator circuit and it is then converted into differential form by using a single input to dual output amplifier. The developed circuit occupies a small area of 0.06 mm^2 and consumes a total power of 44 mW from 1.8 V. The transmission of the generated differential Gaussian monocycle pulse at a rate of 1.4 Gbps through integrated dipole antenna in the same Si-substrate for intrachip communication in future ULSI is verified by simulation and results are presented here.

研究了在硅底物上制造的Sierpinski地毯分形天线的超宽带特性，其耐药性能为2290Ω-CM，79.6Ω-CM和10Ω-CM。在SI底物上获得10 mm距离的天线，在频率范围为2290ω-CM的频率范围内获得了低于10 dB的回报损失，并获得了约14 dB的高传输损失。具有70 ps脉冲宽度的高斯单核细胞脉冲成功地传输在SI底物中，相应的电压增长为23 dB，-26 dB和-39 dB，si抗性为2290Ω-cm，79.6Ω-ω-CM和10ω-cm的SI抗性速度分别是prouss。在接收端传输端和作为模板信号。在本文中，我们介绍了一个新的全面集成的差异高斯单核脉冲发生器，以0.18 pm CMOS技术。这里，差分高斯单核细胞脉冲是由单个区分电路从三角形脉冲产生的，然后通过使用单个输入对双输出放大器将其转换为差异形式。开发的电路占0.06 mm^2的小面积，总功率为44 mW，从1.8 V.以1.4 V的速度以1.4 Gbps的速度通过同一SI-Sibstrate中的集成偶极天线传输，以将来的ULSI在Intrachip通信中传播，以将来的ULSI验证。