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Studies on Logic Design Methods Adaptable to CAD DB

适应CAD DB的逻辑设计方法研究

基本信息

批准号：
10480060
负责人：
KAMBAYASHI Yahiko
金额：
$ 7.42万
依托单位：
KYOTOUNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B).
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-10480060/
关键词：
Logic Optimization Logic Synthesis Transduction Method Error Compensation Method Pass Transistor CMOS Annealing Method Permissible Function 最適論理化 FPGA 拡張許容関数集合論理設計

项目摘要

Reuse of design data and design automation of logic circuits becomes important because logic circuits become to have large and complex structure. Though the CAD database is an indispensable technology to realize reuse of design data, it is difficult to integrate existing design methods and database technology as it is. Thus we have studied and improved design methods of logic circuits suitable for databases, which realize the CAD database. The themes of this research includes an improvement of the transduction method, development of a method for FPGA logic circuit design, development of a reuse technique of logic circuits, and development of a technique for saving power consumption of logic circuits.In 1998, we have developed SSPFs (Super Set of Permissible Functions) that extend CSPFs (Compatible Sets of Permissible Functions) used by the transduction method and increased the degree of freedom in transformation of logic circuits. We also have proposed PSPFDs (Priority based SPFDs) tha … More t generalize the notion of SPFDs representing the logical degree of freedom of FPGA circuits and achieved a 40% reduction in the area of circuits. We have proposed a new algorithm for logic circuit design with saving power consumption that uses 3-state CMOS and realized the function assignment considering saving power consumption.In 1999, we have developed two methods : a method that applies simulated annealing, one of metaheuristics, to the transduction method, and a method of logic optimization based on the notion of PF (Permissible Function) used by the transduction method for a pass transistor logic that is expected to realize more low power consumption circuits than existing CMOS logic.In 2000, first, we have improved the optimization method for pass transistor logic circuits. we have found errors in a book of logic circuits, published more than 35 years ago, that collects minimal circuits calculated by hand by the improved method. Secondly, the development of a optimization method of CMOS logic have progressed. We have applied the method to the pass transistor logic that developed the preceding year for decreasing the number of transistors in logic gates. We also have introduced and applied the transduction method to reduce the number of logic gates. More effective optimization method of logic circuits have been developed by integrating the CMOS logic optimization method and the transduction method. Less

由于逻辑电路变得具有庞大且复杂的结构，因此设计数据的重用和逻辑电路的设计自动化变得重要。虽然CAD数据库是实现设计数据重用不可缺少的技术，但现有的设计方法和数据库技术很难原样集成。由此我们研究并改进了适用于数据库的逻辑电路设计方法，实现了CAD数据库。本研究的主题包括改进换算方法、开发FPGA逻辑电路设计方法、开发逻辑电路的重用技术以及开发节省逻辑电路功耗的技术。1998年，我们开发了SSPF（超级允许函数集），扩展了换算方法所使用的CSPF（兼容的允许函数集）并增加了变换的自由度逻辑电路。我们还提出了 PSPFD（基于优先级的 SPFD），概括了代表 FPGA 电路逻辑自由度的 SPFD 概念，并实现了电路面积减少 40%。我们提出了一种使用三态CMOS的节省功耗的逻辑电路设计新算法，并实现了考虑节省功耗的功能分配。1999年，我们开发了两种方法：一种将元启发式模拟退火应用于换能方法，以及一种基于传输晶体管逻辑的换能方法所使用的PF（允许函数）概念的逻辑优化方法，有望实现比现有CMOS逻辑更低功耗的电路。2000年，我们首先改进了传输晶体管逻辑电路的优化方法。我们在一本 35 多年前出版的逻辑电路书中发现了错误，该书收集了用改进的方法手工计算的最小电路。其次，CMOS逻辑优化方法的开发取得了进展。我们已将该方法应用于前一年开发的传输晶体管逻辑，以减少逻辑门中的晶体管数量。我们还引入并应用了转导方法来减少逻辑门的数量。将CMOS逻辑优化方法与换能方法相结合，发展出更有效的逻辑电路优化方法。较少的