Studies on High-Speed Transaction Machines Utilizing Hardware Concurrency Control Mechanisms

在这个项目的第一年，开始了对体系结构和并发控制机制的基本调查。第二年，通过仿真研究了热点数据的并发控制，并设计了备份机制的硬件。最后一年用于机器的实施和结果的公布。主要研究结果总结如下：1)在响应时间限制的串行性条件下，对处理异构数据和长时间事务的并发控制机制进行了理论研究。2)针对热点数据和非热点数据分别处理的数据库系统，设计了一种新的并行控制方法，这是前人没有研究过的。3)研究了并行事务模型的并发控制机制及其硬件实现。这项研究揭示了该体系结构中死锁增加的问题。提出了解决这一问题的措施，并完成了硬件设计。4)设计了连续备份存储器。由于热点数据备份成本较高，因此开始研发不影响系统运行的硬件同步备份机制。还设计了一个连续备份的磁盘单元。这些机制集成在目标系统的设计中，需要低开销的备份。5)设计了硬件测井系统。由于数据库操作的日志记录占用了某些系统总操作时间的近50%，因此CPU总线的硬件监视器正在开发中。

In the first year of this project, basic surveys on architectures and concurrency control mechanisms were initiated. In the next year, concurrency control for hotspot data were studied through simulations, and the hardware for the backup mechanism was designed. The final year was spent for implementation of the machine and publication of the results.The major results are summarized as follows.1) Theoretical studies were carried out on concurrency control mechanisms which can handle heterogeneous data and long term transactions under the serializability restricted with response time.2) A new method was designed for concurrency control in database systems handling hotspot data and non-hotspot data separately, which had not been studied before.3) A concurrency control mechanism for the parallel transaction model and its hardware implementation were studied. This research disclosed the problem of increased deadlocks in this architecture. A measure for this effect was proposed, and its hardware design was completed.4) A continuously backuped memory was designed. Since the backup cost for hotspot data is expensive, research and development was initiated for a simultaneous hardware backup mechanism which does not slow down system operations. A continuously backuped disk unit was also designed. These mechanisms were integrated in the design of the target system which requires low overhead for backup.5) A hardware logging system was designed. Since logging of database operations occupies nearly 50% of the total operation time of some systems, the hardware monitor for CPU buses is now under development.