Conduction Control in Ultra-High Density Beam-Channel CMOS Transistor

这项研究的目标是实现由两个硅束组成的三维CMOS晶体管，其中侧壁形成一个n沟道和一个p沟道晶体管。结果，基于下面列举的三个主要工作，n沟道晶体管已经成功地运行。将p沟道晶体管添加到该n沟道中，可以形成CNIOS晶体管：(1)场屏蔽器件隔离技术：为了抑制由于束边缘电场集中引起的亚阈值特性的退化，利用自对准多晶硅填充的杂质增强氧化开发了一种新的隔离技术。(2)具有2μm沟道长度的波纹n沟道晶体管：利用各向异性的四甲基氢氧化铵腐蚀剂实现了具有1μm高和50 nm多硅束的n沟道晶体管，具有2-μm沟道长度和31个束流的晶体管在驱动能力上比传统的平面晶体管高5倍。(3)具有0.2-μm沟道长度的束流沟道n-MOS晶体管：采用干法腐蚀在绝缘体上形成高1μm、宽50 nm的束流。利用新开发的自对准栅极绝缘技术，利用杂质增强氧化技术，成功地运行了一种沟道长度为0.2-μm的n-MOS晶体管

The target of this research is to realize three-dimensional CMOS transistor consisting of two silicon beams of which side walls form an n-channel and a p-channel transistors. As the results, n-channel transistors have been successfully operated based on three major works cited below. Adding p-channel transistor to this n-channel, CNIOS transistor can be formed(1) Field shield device isolation technique :To suppress degradation of sub-threshold characteristics due to electric filed concentration at the beam edge, a novel isolation technique is developed utilizing impurity enhanced oxidation with self-aligned polysilicon fill(2) Corrugated n-channel transistor with 2-μm channel length :An n-channel transistor with 1-μm high and 50-nm multiple silicon beams is realized utilizing an inisotropic etchant of tetra methyl ammonium hydroxide, TMAH.A transistor with 2-μm channel length and 31 beams outperforms conventional planar transistor by 5 times in drivability(3) Beam channel n-MOS transistor with 0.2-μm channel length :Beams of 1 μm in height and 50 nm in width are formed on silicon-on-insulator, SOI using dry etching. An n-MOS transistor with 0.2-μm channel length is successfully operated with newly developed self-aligned gate insulation technique utilizing impurity enhanced oxidation