Conduction Control in Ultra-High Density Beam-Channel CMOS Transistor

本研究的目标是实现由两个硅梁组成的三维CMOS晶体管，其侧壁形成一个n沟道和一个p沟道晶体管。因此，基于以下三个主要工作，n沟道晶体管已经成功运行。(1)场屏蔽器件隔离技术：抑制由于束流边缘电场集中而导致的亚阈值特性退化；(2)沟道长度为2 μm的波纹型n沟道晶体管：利用四甲基氢氧化铵（TMAH）的各向同性蚀刻剂实现了1 μm高、50 nm多硅束的n沟道晶体管。具有2 μm沟道长度和31个光束的晶体管的可驱动性是传统平面晶体管的5倍。(3)具有0.2 μm沟道长度的束流沟道n-MOS晶体管：采用干蚀刻技术在绝缘体上硅（SOI）上形成高1 μm、宽50 nm的光束。利用杂质增强氧化的自对准栅极绝缘技术，成功制备了通道长度为0.2 μm的n-MOS晶体管

The target of this research is to realize three-dimensional CMOS transistor consisting of two silicon beams of which side walls form an n-channel and a p-channel transistors. As the results, n-channel transistors have been successfully operated based on three major works cited below. Adding p-channel transistor to this n-channel, CNIOS transistor can be formed(1) Field shield device isolation technique :To suppress degradation of sub-threshold characteristics due to electric filed concentration at the beam edge, a novel isolation technique is developed utilizing impurity enhanced oxidation with self-aligned polysilicon fill(2) Corrugated n-channel transistor with 2-μm channel length :An n-channel transistor with 1-μm high and 50-nm multiple silicon beams is realized utilizing an inisotropic etchant of tetra methyl ammonium hydroxide, TMAH.A transistor with 2-μm channel length and 31 beams outperforms conventional planar transistor by 5 times in drivability(3) Beam channel n-MOS transistor with 0.2-μm channel length :Beams of 1 μm in height and 50 nm in width are formed on silicon-on-insulator, SOI using dry etching. An n-MOS transistor with 0.2-μm channel length is successfully operated with newly developed self-aligned gate insulation technique utilizing impurity enhanced oxidation