Conduction Control in Ultra-High Density Beam-Channel CMOS Transistor

超高密度束沟道 CMOS 晶体管的传导控制

• 批准号: 12555102
• 负责人: SUNAMI Hideo
• 金额: $ 8.32万
• 依托单位: Hiroshima University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12555102/
• 关键词: Beam channel; Field shield; Polysilicon fill; Enhanced oxidation; TMAH; SOI; Self-aligning; CMOS; 鞍型トランジスタ; 素子分離構造; フィールド・シールド; ハンプ電流; 電界集中; 漏洩電流; 鞍型ゲート; 局所酸化法; 不純物濃度依存酸化; プラズマドーピング; 側壁ドーピング

The target of this research is to realize three-dimensional CMOS transistor consisting of two silicon beams of which side walls form an n-channel and a p-channel transistors. As the results, n-channel transistors have been successfully operated based on three major works cited below. Adding p-channel transistor to this n-channel, CNIOS transistor can be formed(1) Field shield device isolation technique :To suppress degradation of sub-threshold characteristics due to electric filed concentration at the beam edge, a novel isolation technique is developed utilizing impurity enhanced oxidation with self-aligned polysilicon fill(2) Corrugated n-channel transistor with 2-μm channel length :An n-channel transistor with 1-μm high and 50-nm multiple silicon beams is realized utilizing an inisotropic etchant of tetra methyl ammonium hydroxide, TMAH.A transistor with 2-μm channel length and 31 beams outperforms conventional planar transistor by 5 times in drivability(3) Beam channel n-MOS transistor with 0.2-μm channel length :Beams of 1 μm in height and 50 nm in width are formed on silicon-on-insulator, SOI using dry etching. An n-MOS transistor with 0.2-μm channel length is successfully operated with newly developed self-aligned gate insulation technique utilizing impurity enhanced oxidation

本研究的目标是实现由两个硅梁组成的三维CMOS晶体管，其侧壁形成n沟道和p沟道晶体管。结果，基于以下引用的三项主要工作，n沟道晶体管已成功运行。在该 n 沟道上添加 p 沟道晶体管，可形成 CNIOS 晶体管(1) 场屏蔽器件隔离技术：为了抑制由于梁边缘电场集中而造成的亚阈值特性劣化，开发了一种利用自对准多晶硅填充的杂质增强氧化的新型隔离技术(2) 沟道长度为 2 μm 的波纹 n 沟道晶体管 ：利用四甲基氢氧化铵 TMAH 各向异性蚀刻剂，实现了高度为 1μm、多条硅梁的 n 沟道晶体管。沟道长度为 2μm、梁数为 31 的晶体管的驱动能力是传统平面晶体管的 5 倍(3) 沟道长度为 0.2μm 的梁沟道 n-MOS 晶体管：梁数为 1 使用干法蚀刻在绝缘体上硅（SOI）上形成高μm、宽50nm的薄膜。采用新开发的利用杂质增强氧化的自对准栅极绝缘技术成功运行沟道长度为 0.2μm 的 n-MOS 晶体管

项目成果

H.Sunami: "A Three-Dimensional MOS Transistor Formation Technique with Crystallographic Orientation-Dependent TMAH Etchant"SENSORS and ACTUATORS A : PHYSICAL. (in press). (2004)

H.Sunami：“采用晶体取向相关的 TMAH 蚀刻剂的三维 MOS 晶体管形成技术”传感器和执行器 A：物理。

片上 朗: "ビームチャネルMOSFETにおけるゲート形成プロセス"第62回応用物理学会学術講演会予稿集. 688 (2001)

Akira Katakami：“束沟道MOSFET中的栅极形成过程”第62届日本应用物理学会年会记录688（2001）。

A.Takase: "Field-Shield Trench Isolation with Self-Aligned Field Oxide"Jpn.J.Appl.Phys.. 42. 2100-2105 (2003)

A.Takase：“采用自对准场氧化物的场屏蔽沟槽隔离”Jpn.J.Appl.Phys.. 42. 2100-2105 (2003)

A.Takase: "Field-Shield Trench Isolation with Self-Aligned Field Oxide"Jap. J. Appl. Phys.. 42,4-B. NA (2003)

A.Takase：“采用自对准场氧化物的场屏蔽沟槽隔离”Jap。

H.Sunami: "Fundamental Characteristics of Crystallographic Orientation-Dependent TMAH Etching and Its Application To Three-Dimensional Silicon"Sensors and Actuators A : Physical. NA. NA (2003)

H.Sunami：“晶体取向相关的 TMAH 蚀刻的基本特性及其在三维硅中的应用”传感器和执行器 A：物理。