Study on High-Performance Low-Power Chip Multiprocessors

高性能低功耗片式多处理器的研究

• 批准号: 13480077
• 负责人: SAKAI Shuichi
• 金额: $ 9.54万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2001
• 资助国家: 日本
• 起止时间: 2001 至 2003
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13480077/
• 关键词: Chip Multiprocessor; Low Power Architecture; Coherent Cache; Power Simulator; Speculative Multithreading; Performance Evaluation; Thread Prediction; Optimizing Compiler; 省電力; スレッド投機実行; CPU; 分岐予測; マルチスレッデイング; 投機処理; 命令スケジューリング; メモリバイオレーション

We studied high-performance low-power chip multiprocessors and obtained the following results.(1) System level power reductionWe examined the power estimation framework which calculates the power consumption from the architecture description. The framework has high extensibility and flexibility. It can reduce the cost of designing low power processor chips. In addition, it makes easy the evaluations of the power reduction techniques. We also studied the elementary technologies for power reduction of chip multiprocessors. One of the most important elements is a cache, where we proposed the power reduction technique, evaluated it and showed its effectiveness.(2) Performance improvement by speculative multithreadingWe intensively studied the speculative multithreading, for improving the performance of sequential programs and extracting the maximum power of chip multiprocessors. We proposed and evaluated the innovative speculative multithreading on the following points (1) speculative execution for dependent activities; (2) thread fusion for reducing thread invocation/termination overhead; (3) register communication mechanisms suitable for thread speculations; (4) prediction mechanisms for efficient speculations; and (5) compiler support. For detailed design and feasibility studies, we have built a cycle level simulator of the chip multiprocessor and a C compiler for it, and closely evaluated each technology. The results showed the substantial performance improvement.

我们研究了高性能低功耗片上多处理器，得到了以下结果。(1)系统级功耗降低我们研究了从架构描述计算功耗的功耗估计框架。该框架具有很高的可扩展性和灵活性。它可以降低低功耗处理器芯片的设计成本。此外，它使容易的功率降低技术的评估。研究了降低单片多处理器功耗的基本技术。其中最重要的元素之一是缓存，我们提出了降低功耗的技术，评估它，并显示其有效性。(2)基于推测多线程的性能改进为了提高顺序程序的性能，充分发挥片上多处理器的性能，我们对推测多线程进行了深入研究。我们提出并评估了以下几点创新的推测多线程（1）依赖活动的推测执行;（2）线程融合，以减少线程调用/终止开销;（3）寄存器通信机制，适合线程推测;（4）预测机制，有效的推测;（5）编译器支持。详细的设计和可行性研究，我们已经建立了一个周期级模拟器的芯片多处理器和C编译器，并密切评估每一种技术。结果表明，性能得到了实质性的改善。

项目成果

Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: "Evaluations of Instruction Scheduling on Speculative Multithreading (in Japanese)"2001-ARC-144. Vol.2001, No.24. 135-140 (2001)

Daisuke Tashiro、Niko Demus Barli、Shuichi Sakai、Hidehiko Tanaka：“推测多线程指令调度的评估（日语）”2001-ARC-144。

Niko Demus Barli, Daisuke Tashiro, Shuichi Sakai, Hidehiko Tanaka: "Dynamic Thread Extension for Speculative Multithreading Architecture"2001-ARC-144. Vol.2001, No.23. 129-134 (2001)

Niko Demus Barli、Daisuke Tashiro、Shuichi Sakai、Hidehiko Tanaka：“推测多线程架构的动态线程扩展”2001-ARC-144。

Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: "Compiler-Assisted Thread Level Control Speculation"Proc.Euro-par 2003. 2003. 603-608 (2003)

Hideyuki Miura、Luong Dinh Hung、Chitaka Iwama、Daisuke Tashiro、Niko Demus Barli、Shuichi Sakai、Hidehiko Tanaka：“编译器辅助线程级别控制推测”Proc.Euro-par 2003. 2003. 603-608 (2003)

Daisuke Iizuka, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: "Proposal and Evaluations on Efficient Value Predictions (in Japanese)"IPSJ Transactions on ACS1. Vol.SIG6, no. ACSI,. 65-75 (2003)

Daisuke Iizuka、Niko Demus Barli、Shuichi Sakai、Hidehiko Tanaka：“有效价值预测的提案和评估（日语）”ACS1 上的 IPSJ 交易。

Luong Dinh Hung, Hideyuki Miura, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: "A Hardware/Software Approach for Thread Level Control Speculation"2002-ARC-149. Vol.2002, No.1. 67-72

Luong Dinh Hung、Hideyuki Miura、Chitaka Iwama、Daisuke Tashiro、Niko Demus Barli、Shuichi Sakai、Hidehiko Tanaka：“线程级别控制推测的硬件/软件方法”2002-ARC-149。