Study on High-Performance Low-Power Chip Multiprocessors

本文对高性能低功耗片上多处理器进行了研究，取得了以下成果：(1)系统级功耗降低研究了从体系结构描述计算功耗的功耗估算框架。该框架具有很高的可扩展性和灵活性。它可以降低低功耗处理器芯片的设计成本。此外，它还使功率降低技术的评估变得容易。我们还研究了芯片多处理器功耗降低的基本技术。其中最重要的元素之一是缓存，我们在缓存中提出了一种降低功耗的技术，对其进行了评估，并展示了其有效性。(2)通过推测多线程提高性能我们对推测多线程进行了深入研究，以提高顺序程序的性能，获取芯片多处理器的最大功耗。我们从以下几个方面提出并评估了创新的推测多线程：(1)依赖活动的推测执行；(2)减少线程调用/终止开销的线程融合；(3)适合线程推测的寄存器通信机制；(4)高效推测的预测机制；以及(5)编译器支持。为了进行详细的设计和可行性研究，我们构建了芯片多处理器的循环级模拟器和C编译器，并对每种技术进行了仔细的评估。结果表明，性能有了很大的提高。

We studied high-performance low-power chip multiprocessors and obtained the following results.(1) System level power reductionWe examined the power estimation framework which calculates the power consumption from the architecture description. The framework has high extensibility and flexibility. It can reduce the cost of designing low power processor chips. In addition, it makes easy the evaluations of the power reduction techniques. We also studied the elementary technologies for power reduction of chip multiprocessors. One of the most important elements is a cache, where we proposed the power reduction technique, evaluated it and showed its effectiveness.(2) Performance improvement by speculative multithreadingWe intensively studied the speculative multithreading, for improving the performance of sequential programs and extracting the maximum power of chip multiprocessors. We proposed and evaluated the innovative speculative multithreading on the following points (1) speculative execution for dependent activities; (2) thread fusion for reducing thread invocation/termination overhead; (3) register communication mechanisms suitable for thread speculations; (4) prediction mechanisms for efficient speculations; and (5) compiler support. For detailed design and feasibility studies, we have built a cycle level simulator of the chip multiprocessor and a C compiler for it, and closely evaluated each technology. The results showed the substantial performance improvement.