Research on Multithreaded Massively Parallel Computers

本课题的研究成果如下：1.多线程大规模并行计算机的性能评价用EM-4并行计算机和RWC-1并行计算机对多线程大规模并行计算机的性能进行了评价。对系统中的同步机制、流水线结构、消息处理机制等并行原语进行了评价，并对系统的整体性能进行了测试。基准测试的例子有（1）基数排序，（2）稀疏矩阵计算和（3）密集矩阵计算，如Linpack。测试结果表明，所提出的多线程体系结构对于各种应用程序都是相当有效的.多线程并行计算机I/O系统的提出和性能评价提出了多线程大规模并行计算机I/O系统，并使用一个真实的系统进行了评价。结果表明，在穆尔模型下，可以构造高效的并行I/O系统 关于我们 3.一种新的处理器体系结构的提出和早期评估作为21世纪器件技术的一种新的处理器体系结构，我们提出了片上多处理器体系结构和集成处理器和存储器的体系结构。特别是对于高性能计算，我们研究了一种结构，其中单个LSI包含一个处理器和一个高速存储器，而大容量存储器在其外部实现，通过使用内部存储器作为临时存储器，这种结构可以隐藏存储延迟。在MIPS R10000体系结构的基础上，设计了基于该体系结构的处理器的基础部分，并构造了一个模拟器。我们使用Liver-more Kernel和Linpack等基准进行了早期评估。评价结果表明，该系统获得了接近理想的性能，可以说为未来高性能混凝土（持续性能100 TFLOPS）奠定了部分基础技术.大规模并行计算机互连网络的提出和评价我们研究了大规模并行计算机互连网络的结构，提出了一种缓冲区控制方法，它可以大幅度地提高通信吞吐量。上述结果已在英文期刊、日文期刊和会议上发表，并得到了许多好评。少

The research results of this projects are listed below.1. Performance evaluations of multithreaded massively parallel computersPerformance of multithreaded massively parallel computers were evaluated by using a parallel computer EM-4 and a massively parallel computer RWC-1. Parallel primitives such as synchronization mechanisms, pipeline structure, message handling mechanisms were evaluated and the whole system performance was examined. Examples of benchmarks were (1) radix sort, (2) sparse matrix calculations and (3) dense matrix calculations such as Linpack. The evaluation results showed that the proposed multithreaded architecture is fairly effective for the wide variety of applications.2. Proposal and performance evaluations of I/O systems for multithreaded parallel computersThe I/O systems for multithreaded massively parallel computers were proposed and evaluted by using a real system. The evaluation showed that we can construct efficient parallel I/O system under the model of mul … More tithreading.3. Proposal and early evaluations of a new processor architectureAs a new processor architecture exploiting device technologies in 21st century, we proposed both an on-chip multiprocessor architecture and an architecture integrating a processor and memories. Especially for the high-performance computing, we examined the architecture where a single LSI contains a processor and a high-speed memory and the large storage is implemented outside of it. By using the internal memory as a temporal storage, this architecture can hide memory latency. It can also provide data fairly quickly if they are reused in the LSI.The fundamental part of the processor based on the architecture was designed on the base of MIPS R10000 architecture, and a simulator was constructed. We made early evaluations using benchmarks such as Liver-more Kernel and Linpack. The evaluation results showed that the nearly ideal performance was obtained, and we can say that the part of basic technologies for the future HPC (sustainted performance 100 TFLOPS) was established.4. Proposal and evaluations of interconnection networks for massively parallel computersWe examined the architecture of interconnection networks for massively parallel computers, and proposed the buffer control method which can drastically increase communication throughput.The results described above have been presented in English journals, Japanese journals and conferences, and have got a lot of favorable criticisms. Less