Study on Low Power Technologies for Next Generation Microprocessors

为实现下一代低功耗微处理器，我们的研究成果如下：首先，我们建立了两种周期级模拟器，作为定量评估的基础：片上多处理器模拟器和集群超标量处理器模拟器。接下来，我们开展了两类研究：（1）系统级低功耗技术研究：以及（2）研究在降低功耗的同时减轻软错误的技术。作为系统级低功耗技术，本文主要研究了以下几个方面的问题：1）基于分支预测器的热路径检测器; 2）改进基于特征的程序阶段检测机制;通过OS支持动态估计线程级并行性1.4）通过串行化片上总线来降低功率1.5）片上非均匀共享高速缓存多处理器作为用于通过降低功耗来减轻软错误的技术，我们研究了以下内容：2.1）利用水平和垂直奇偶校验的软错误减轻2.2）内容可寻址存储器上的软错误减轻2.3）针对处理异常和软错误的措施我们集成了上述技术，并展示了在下一代处理器上降低功耗和提高效率的方法。

The followings are the research products for realizing next generation low power microprocessors.First, we built up two types of cycle level simulators for the base of quantitative evaluations : the chip multiprocessor simulator and the clustered superscalar processor simulator. Next, we carried out two types of researches : (1) researches on system level low power technologies : and (2) researches on technologies for mitigating soft errors with reducing power consumption.As system level low power technologies, we studied the followings.1.1) the hot path detector exploiting branch predictors1.2) improving program phase detection mechanisms based on signatures1.3) dynamic estimation of thread level parallelism by OS support1.4) power reduction by serializing on-chip buses1.5) non-uniform shared cache on chip multiprocessorsAs technologies for mitigating soft errors with reducing power consumptions, we studied the followings.2.1) soft error mitigation exploiting horizontal and vertical parities2.2) soft error mitigation on content addressable memories2.3) measures against process anomalies and soft errorsWe integrate the above technologies and showed the methodologies for reducing power and gaining efficiency on the next generation processors.