Study on Low Power Technologies for Next Generation Microprocessors

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The followings are the research products for realizing next generation low power microprocessors.First, we built up two types of cycle level simulators for the base of quantitative evaluations : the chip multiprocessor simulator and the clustered superscalar processor simulator. Next, we carried out two types of researches : (1) researches on system level low power technologies : and (2) researches on technologies for mitigating soft errors with reducing power consumption.As system level low power technologies, we studied the followings.1.1) the hot path detector exploiting branch predictors1.2) improving program phase detection mechanisms based on signatures1.3) dynamic estimation of thread level parallelism by OS support1.4) power reduction by serializing on-chip buses1.5) non-uniform shared cache on chip multiprocessorsAs technologies for mitigating soft errors with reducing power consumptions, we studied the followings.2.1) soft error mitigation exploiting horizontal and vertical parities2.2) soft error mitigation on content addressable memories2.3) measures against process anomalies and soft errorsWe integrate the above technologies and showed the methodologies for reducing power and gaining efficiency on the next generation processors.