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Moving Picture Codec LSI for High Definition TVs

用于高清电视的运动图像编解码器LSI

基本信息

批准号：
15560306
负责人：
ENOMOTO Tadayoshi
金额：
$ 2.37万
依托单位：
CHUO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2004
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-15560306/
关键词：
LSI prosessor power disspation low power techniqe leakage current motion estimation algorithm moving picture encoding breaking off search algorithm 固体撮像素子高性能化技術

项目摘要

(1) Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.(2) High speed motion vector estimation methods such as "multi-step breaking off search algorithm" etc. have been developed. To reduce power dissipation of an absolute difference accumulator (ADA) for motion estimation (NIE), a fast ME algorithm called a "Breaking-Off Search Adaptively minimizing number of block matchings (BOSA)" algorithm was developed. BOSA can improve processing speed of the full-search (FS) method by a factor of more than 10, while maintaining visual quality of the FS method.(3) At clock frequency of 160 MHz and supply voltage of 1.4 V the power dissipation of a 0.18-μm CMOS absolute difference accumulator (ADA) using BOSA and a gated-clock pulse scheme was reduced to 30 μW that was about 1/1,000,000 that of the same ADA implementing FS.(4) In order to reduce leakage current, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 1-Kb SRAM incorporating the SVL circuit was 65.7 nW that was about 20 % of that (321 nW) of an equivalent conventional 1-Kbit SRAM. The active power of this new SRAM was 625 μW, 95 % of that of the equivalent conventional 1-Kbit SRAM (at VDD = 1.8 V, fc = 100 MHz). The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.

(1)本研究的相关技术，如运动图像编码和解码，高速信号处理，低功耗和低泄漏电流的LSI等进行了研究。(2)高速运动矢量估计方法如“多步中断搜索算法”等已经被开发出来。为了降低运动估计绝对差累加器（ADA）的功耗，提出了一种快速运动估计算法--“中断搜索自适应最小块匹配数（BOSA）”算法。BOSA可以将全搜索（FS）方法的处理速度提高10倍以上，同时保持FS方法的视觉质量。(3)在时钟频率为160 MHz、电源电压为1.4V时，采用BOSA和门控时钟脉冲方案的0.18 μm CMOS绝对差累加器（ADA）的功耗降低到30 μW，约为采用FS的ADA的1/1，000，000。(4)为了减小漏电流，研制了一种可根据需要向有源负载电路提供最大直流电压或在待机模式下降低向负载电路提供的直流电压的自控制电压电平（SVL）电路。该SVL电路可以在芯片面积和速度方面以最小的开销大幅降低CMOS逻辑电路和SRAM的待机泄漏功率。采用SVL电路的1-KbSRAM的待机功率为65.7 nW，约为等效的传统1-KbSRAM的待机功率（321 nW）的20%。在VDD = 1.8V，fc = 100 MHz时，该SRAM的有效功率为625 μW，是传统1 Kbit SRAM的95%。这种新型SRAM的读访问时间为553 psec，仅比同等的传统1-Kb SRAM长2.6%。