Moving Picture Codec LSI for High Definition TVs

(1)研究了运动图像编解码、高速信号处理、lsi低功耗低漏电流等相关技术。(2)高速运动矢量估计方法，如“多步中断搜索算法”等得到了发展。为了降低运动估计中绝对差分累加器（ADA）的功耗，提出了一种快速的运动估计算法——“断开搜索自适应最小化块匹配数（BOSA）”算法。BOSA可以在保持全搜索（FS）方法的视觉质量的同时，将全搜索（FS）方法的处理速度提高10倍以上。(3)在时钟频率为160 MHz、电源电压为1.4 V时，采用BOSA和门时钟脉冲方案的0.18 μm CMOS绝对差累加器（ADA）的功耗降至30 μW，约为实现FS的相同ADA的1/ 100万。(4)为了减小泄漏电流，设计了一种电压电平自控电路，该电路可以根据要求向有源负载电路提供最大直流电压，也可以在待机状态下降低负载电路的直流电压。这种SVL电路可以大大降低CMOS逻辑电路和sram的待机泄漏功率，在芯片面积和速度方面的开销最小。包含SVL电路的1kb SRAM的待机功率为65.7 nW，约为等效传统1kbit SRAM （321 nW）的20%。这种新型SRAM的有功功率为625 μW，是同等传统1 kbit SRAM （VDD = 1.8 V, fc = 100 MHz）的95%。这种新的SRAM的读访问时间为553 psec，也就是说，只比同等的传统1 kb SRAM长2.6%。

(1) Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.(2) High speed motion vector estimation methods such as "multi-step breaking off search algorithm" etc. have been developed. To reduce power dissipation of an absolute difference accumulator (ADA) for motion estimation (NIE), a fast ME algorithm called a "Breaking-Off Search Adaptively minimizing number of block matchings (BOSA)" algorithm was developed. BOSA can improve processing speed of the full-search (FS) method by a factor of more than 10, while maintaining visual quality of the FS method.(3) At clock frequency of 160 MHz and supply voltage of 1.4 V the power dissipation of a 0.18-μm CMOS absolute difference accumulator (ADA) using BOSA and a gated-clock pulse scheme was reduced to 30 μW that was about 1/1,000,000 that of the same ADA implementing FS.(4) In order to reduce leakage current, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 1-Kb SRAM incorporating the SVL circuit was 65.7 nW that was about 20 % of that (321 nW) of an equivalent conventional 1-Kbit SRAM. The active power of this new SRAM was 625 μW, 95 % of that of the equivalent conventional 1-Kbit SRAM (at VDD = 1.8 V, fc = 100 MHz). The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.